International Business Machines Corporation

Gottfried Andreas Goldrian

Norbert Schumacher

Bernd Leppla

Volker Rudolph

Thomas Anthony Gregg

Francois Abel

Ronald Pete Luijten

Manfred Ries

David Arlen Elko

Alan Frederic Benner

Steven N Goss

Dietrich J Bahr

Audrey A Helffrich

Ingemar Holm

Helmut Kohler

Dieter F Wendel

Hans-Werner Tast

Otto Andreas Torreiter

Arnold Blum

Antonius Paulus Engbersen

Ambrose A Verdibello, Jr

Volker W Zimmermann

Ludwig Fischer

Markus Cebulla

Joseph A Williams

Wilhelm G Spruth

Manfred Wohnsdorf

Karl-Heinz Burckardt

Manfred E Nitschke

Antonius Engberson

Jurgen Margner

Wolfgang Kumpf

A liquid cooling device comprises a heat spreader disposed along a plurality of memory modules on a dual in-line memory module (DIMM), a cold rail block extending along the heat spreader and a compressible thermal adapter interleaved between the cold rail block and the memory modules. The thermal adapter is compressible in a direction perpendicular to the plane of the DIMM board, thus allowing the components of the cooling device to be moved and adjusted relative to each other in a direction perpendicular to the plane of the DIMM. In a preferred embodiment, matching smooth surfaces of adjacent components within the cooling device are collated with a lubricant, thus permitting a low-friction gliding of these components relative to each other and allowing the DIMM to be easily removed from the cooling device and to be replaced without effort and without tooling.

Liquid DIMM cooling device

A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

Switching arrangement and method with separated output buffers

A system for cooling processor assembly is disclosed which comprises a printed circuit board (PCB) with a plurality of heat emitting electronic components and a housing for each PCB with a heat collector. The heat collector is constructed in one-piece material covering the plurality of heat emitting electronic components through heat collecting areas with different heights adapted to the different heights of the electronic components as regard to the PCB surface wherein the heat collecting areas being in thermal contact with the electronic components.

Housing used as heat collector

A system for cooling processor assembly is disclosed which comprises printed circuit boards (PCB) with a plurality of heat emitting electronic components, and a housing for each PCB with a heat sink covering at least partly the heat emitting electronic components. The housing comprises a base portion to which are transferred heat emitted by the electronic components. Furthermore, the system for cooling processor comprises a cooling plate on which are fixed in series the different PCBs by directly positioning the base portion of the housings onto the cooling plate. The housings for each PCB system include at their base portions clamps to be inserted into corresponding guiding holes of the cooling plate when a PCB together with its housing is positioned onto the cooling plate at a specific therefor dedicated place defined by the guiding holes. Advantageously, the PCB together with its housing is pressed against the cooling plate alongside the base portion when fixed onto the cooling plate allowing thermal coupling between the housing and the cooling plate and a hot plugging of the PCB onto the cooling plate without requiring interrupting the cooling process applied to the cooling plate.

Low cost liquid cooling

Discloses a switching arrangement for packets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each input port a set of output buffers is arranged, each set comprising an output buffer for each output port.

The present invention relates to a buffered crossbar switch which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Buffered crossbar switch

A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch

A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

Method and an integrated circuit for performing a test

A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Combined and data compressed FIFO based arbitration for a non-blocking switch

The present invention relates to a buffered crossbar switch and its method of operation which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Buffered crossbar switch and its method of operation

The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements () having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.

Control logic implementation for a non-blocking switch network

The present invention relates to a method of operating a crossbar switch () having a control logic () and n input ports (i, . . . , i_n-) and m output ports (o, . . . , o_m-), wherein information packets of p different priority levels are routed from said n input ports (i, . . . , i_n-) to said m output ports (o, . . . , o_m-). Within said control logic (), a pool (CRA) of buffers (CRA, CRA, . . . ) is provided for each crosspoint () for temporarily storing address information related to said information packets.

Method of operating a crossbar switch

The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.

Method of operating a buffered crossbar switch

The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device 'oscillator' but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

Digital frequency correction

A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits. Both signals are ANDed. Thus, in the resulting signal a pulse emerge at every positive transition of the oscillator clocks when the phase alignment of the clock signals is closer than the width of the transition pulse. When the alignment is bad&mdash;no signal will be produced.

Method of switching between a first and second clock signal by establishing a trigger time in which both signals are considered to be substantially in-phase

Growing community of inventors

Boeblingen, Germany

Gottfried Andreas Goldrian