Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Symetrix Corporation

Gota Kano

Hitoo Iwasa

Carlos Alberto Paz De Araujo

Larry D McMillan

Iwao Teramoto

Hiromitsu Takagi

Koji Arita

Shinichiro Hayashi

Joseph D Cuchiaro

Susumu Koike

Shotaro Umebachi

Yasuhiro Shimada

Hideo Nagai

Tatsuo Morita

Michael C Scott

Jolanta Bozena Celinska

Akihiro Matsuda

Morio Inoue

Jeffrey W Bacon

Satoshi Teramoto

Naoyuki Tsuda

Atsushi Nagashima

Shutaro Nanbu

Yoshio Yamaguchi

A thin film of ferroelectric layered superlattice material in a flat panel display device is energized to selectively influence the display image. In one embodiment, a voltage pulse causes the layered superlattice material to emit electrons that impinge upon a phosphor, causing the phosphor to emit light. In another embodiment, an electric potential creates a remanent polarization in the layered superlattice material, which exerts an electric field in liquid crystal layer, thereby influencing the transmissivity of light through the liquid crystal. The layered superlattice material is a metal oxide formed using an inventive liquid precursor containing an alkoxycarboxylate. The thin film thickness is preferably in the range 50-140 nm, so that polarizabilty and transparency of the thin film is enhanced. A display element may comprise a varistor device to prevent cross-talk between pixels and to enable sudden polarization switching. A functional gradient in the ferroelectric thin film enhances electron emission. Two ferroelectric elements, one on either side of the phosphor may be used to enhance luminescence. A phosphor can be sandwiched between a dielectric and a ferroelectric to enhance emission.

Ferroelectric flat panel displays

Metal organic precursor compounds are dissolved in an organic solvent to form a nonaqueous liquid precursor. The liquid precursor is applied to the inner envelope surface of a fluorescent lamp and heated to form a metal oxide thin film layer. The metal oxide thin film layer may be a conductor, a protective layer or provide other functions. The films have a thickness of from 20 nm to 500 nm. A conductive layer comprising tin-antimony oxide with niobium dopant may be fabricated to have a differential resistivity profile by selecting a combination of precursor composition and annealing temperatures.

Fluorescent lamp and method of manufacturing same

A new method (P200) is provided for making magnesium oxide layers (122) in plasma displays (100). A magnesium carboxylate liquid precursor solution is applied to a display panel (102), dried, and annealed to yield a solid magnesium oxide layer (122) having excellent electro-optical performance.

Method of forming magnesium oxide films on glass substrate for use in

A dual gate Schottky barrier gate GaAs FET with improved cross-modulation characteristics when used in a UHF gain controlling tuner, having a value of 40 mA or smaller of a drain to source saturation current, the improvement of the FET is that length of a second gate which is disposed between a first gate and a drain is 1.5 .mu.m or longer.

Field effect transistor

A novel self-align type method of making an FET with a very short gate length and a good high frequency characteristic, and a low noise characteristic, the method comprising the steps of:

Method of making FET utilizing shadow masking and diffusion from a doped

In the process of forming a thermal oxide film or heat treatment of an oxide film in making a semiconductor device comprising a compound semiconductor of arsenic, the semiconductor is handled in an atmosphere containing arsenic oxide vapor in order to prevent evaporation of the arsenic tri-oxide in the thermal oxidation film or the oxide film under heat treatment, thereby to form a thermal oxide film having good chemical stability and good electrical characteristics, or to improve the oxide film so as to have good chemical stability and good electrical characteristics.

Selective thermal oxidation of As-containing compound semiconductor

A new type of nonvolatile static read/write memory cell constructed with one MOS transistor and one MNOS transistor (4) is disclosed. The MNOS transistor (4) and the MOS transistor (3) together with a load resistor are complementary combined to offer binary states in the .LAMBDA.-shaped I-V curve for memory operation under normal power supply. Upon power failure, the MNOS transistor (4) acts as a backing-up element for nonvolatility. By impressing a control pulse on the drain of the MNOS transistor (4) the MNOS transistor changes from the depletion mode to the enhancement mode, thereby storing the last memory contents before the power failure. The stored nonvolatile memory contents can be easily retrieved. Thus a small size static random access memory is provided. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.

Semiconductor memory device

A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the above-mentioned way, respectively, of the other FET. The device is characterized in that each FET has each back-gate electrode region behind the channel. Preferably, such back-gate regions are high-doped diffused regions. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage. Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate comprising FETs with back-gate electrode, it is not only fit to be highly integrated but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses, with low Vth2 value.

Negative-resistance semiconductor device

The invention discloses a heterojunction Type GaAs field-effect transistor of the type in which a channel region consists of an n-type GaAs layer with a higher mobility and a gate region consists of a p-type Ga.sub.1-y Al.sub.y As layer which is grown heteroepitaxially. The length of the gate is of the order of microns, and a gate, source and drain electrodes are self-aligned. The gate region is etched in the form of a mushroom with the use of an etchant which etched the GaAlAs layer and the Ga-As layer at different etching rates so that the gate, source and drain electrodes may be formed by only one vacuum deposition of a metal such as aluminum.

Junction gate type GaAs field-effect transistor and method of forming

A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the abovementioned way, respectively, of the other FET. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon over a fairly wide range of applied voltage. Since this device is, as seen from outside as one device, a two-terminal device constituted on a single substrate, it is not only fit to be highly integrated, but also able to produce a state of virtually zero value of cut-off current. Consequently, this device can be utilized for switching, memorization, large amplitude oscillation, and other various uses.

A negative resistance device formed by series-connection of a complementary pair of insulated gate type FETs (field effect transistors), the source of the FETs being connected to each other and the gates of each of the FETs being connected to the respective drain of the other FET at least one FET having a double layered gate insulation film under the gate electrode, thereby forming a non-volatile memory element. The negative resistance device acquires or loses negative resistance characteristics by responding to signals to the gates, thereby memorizing the signals and resulting in a highly efficient memory which requires little power in writing-in, erasing and memory-holding.

Negative resistance device

Across a D.C. power source 1, a load 2, a switching element 4, such as a transistor having a control electrode c (base), and a voltage detection means 5, such as a resistor, are connected in series, and a known negative resistance device 6, having two terminals 31 and 32, is connected by its one terminal 32 to said control electrode c of the switching element 4 and by its other terminal 31 to one end of said series resistor 5 which one end is opposite to that connected to said switching element (4), wherein said negative resistance device 6 comprises, as shown in FIG 2, known complementary connection of a depletion mode n-channel field-effect transistor (FET) and a depletion mode p-channel FET. The FETs are connected from source to source, and from the gate of each to the drain of the other so that when an overcurrent to the load 2 or an overvoltage at the voltage source 1 occurs, voltage across said resistor 5 exceeds a preset value, the negative resistance device 6 is cut-off, thereby cutting off the switching element 4.

Apparatus to prevent overcurrent or overvoltage

A touch-operation semiconductor switch is constituted by employing a switching device and a semiconductor negative resistance device comprising a complemetary connection of a depletion mode n-channel junction type field-effect transistor (hereinafter: FET) and a depletion mode p-channel junction type FET, both FETs being connected by source to source to each other, and by each gate to each drain of the other FET, and a touching terminal is connected to said common connected sources, so that the on-off state of the negative resistance device is inversed when the touching terminal is touched by human body.

Touch-operation switch

Both source-electrodes (S1 and S2) or both drain-electrodes of a pair of field-effect transistors (FETs) (F1 and F2) of n-channel type and p-channel type, respectively, both to be electrically actuated in a depletion mode are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, through a variable resistance element (F3) inbetween, whereby the pair of FETs (F1 and F3) are series-connected through the variable resistance element (F3) inbetween, the gate-electrode (g1 or g2) of each FET is connected to the drain-electrode (d2 or d1) or the source-electrode of the other FET (F2 or F1) that is not connected to the variable resistance element (F3), and a pair of external terminals (1 and 2) are connected to said gate electrodes (g1, g2) those are connected to said drain electrodes (d2 and d1) or source electrodes. When a voltage of specified range is applied across both non-series-connected electrodes, i.e., the two external terminals, the resulting voltage-current characteristic presents a so-called dynatron-type characteristic, producing a negative-resistance phenomenon, and a curve of voltage-current characteristic changes responding to the value of control signal to the variable resistance element. Since this device is a negative resistance of variable characteristic this device can be utilized for switching, signal relaying, memorization and other various controlling or data processing uses.

A series connection comprising a transistor (4) and a light-emitting diode (3) is connected across a D.C. power source (+Vcc), and one end of a negative-resistance device (1) is connected to the base of said transistor (4) and the other end thereof is connected to an end of said light-emitting diode (3), which last-mentioned one end is connected to the D.C. power source (+Vcc). The circuit constituted as above memorizes an occurence of voltage drop which enables bistable switching in the negative-resistance device, thereby energizing the light emitting diode to light. The circuit can be used to indicate voltage lowering or interruption of an A.C. power supply, or weakening of a battery.

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Kyoto, Japan

Gota Kano