Nec Corporation

Pioneer Corporation

Goro Ueda

Toru Kimura

Hiroshi Shiba

Yoji Hirano

When power is turned on, dummy output information stored in a non-volatile memory is issued to the digital signal processing circuit. In a dummy data processing block, and in a line memory holding data in the horizontal direction, dummy data inputted from outside is inserted into a one-line video data processed at an input signal processing block, based on the dummy output information. In this way, the video data is revised into data that is appropriate for each display, based on the dummy output information. Then the one-line video data including the dummy data is inputted into the output signal processing block, and is latched by the output signal processing block, and outputted to each of the data drivers as a data driver output signal, at the same time.

Signal processing circuit and signal processing method of digital display

A subfield coding circuit which subfield-converts R, G, and B image data for producing subfield-converted image data, includes (a) a multiplexer which multiplexes R, G, and B image data, (b) a memory such as a static random access memory (SRAM), including a single lookup table through which the R, G, and B image data is converted into subfield-coded data in time-division, and (c) a demultiplexer which demultiplexes the subfield-coded data to output subfield-coded R, G, and B image data.

Subfield coding circuit and subfield coding method

A sample-and-hold circuit configured with a low source voltage for assuring low power consumption. An input signal and an output signal are coupled to one side and to the other side of a current mirror circuit. The input signal is sample-held by a differential circuit adapted to cause the current to flow a desired current to the current mirror circuit and to perform switching of the current mirror circuit and sample clocks entered to the differential circuit. The sample-holding operation is feasible even with a lower voltage source.

Sample-and-hold circuit operable at a low voltage

A sample-and-hold circuit comprises an analog signal control circuit for supplying a potential of an input signal to one end of a hold capacitor, a first transistor having a base connected to the one end of the hold capacitor and operating in an emitter follower fashion, an amplifier having a second transistor having a base connected to an emitter of the first transistor, and a leak current compensating circuit including a third transistor having an emitter connected to a collector of the first transistor and a current mirror circuit for supplying to the base of the first transistor the same current as a base current of the third transistor.

Sample-and-hold circuit including a robust leakage current compensating

A gamma correcting circuit has a plurality of differential amplifiers having respective input terminals for being supplied with a video signal and respective output terminals connected in common. At least one of the differential amplifiers comprises differential pairs of transistors including transistors whose bases are not connected to the input terminal, emitters are connected to respective resistors, and collectors are connected in common. A plurality of individually energizable and de-energizable external reference voltage supplies are connected to the bases of the transistors whose bases are not connected to the input terminal.

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Tokyo, Japan

Goro Ueda