Hitachi, Ltd.

Hitachi Device Engineering Co., Ltd.

Other

Texas Instruments Corporation

Renesas Technology Corp.

Hitachi Vlsi Engineering Corp.

Elpida Memory, Inc.

Rising Silicon, Inc.

Vlsi Engineering Corporation

Hitachi Ltd, of Japan

Goro Kitsukawa

Takesada Akiba

Kiyoo Itoh

Ryoichi Hori

Takao Watanabe

Takayuki Kawahara

Yoshiki Kawajiri

Hiroshi Otori

Yutaka Kobayashi

William R McKee

Jeffrey E Koelling

Troy H Herndon

Noriyuki Homma

Masayuki Nakamura

Yasushi Kawase

Katsuhiro Shimohigashi

Tsugio Takahashi

Takahide Ikeda

Hideaki Uchida

Shinji Nakazato

Masahiro Yamamura

Nobuo Tanba

Masayuki M Nakamura

Yoshikazu Saito

Kazumasa Yanagisawa

Kunihiko Yamaguchi

Michihiro Mishima

Masashi Horiguchi

Noriyuki Honma

Masakazu Aoki

Hitoshi Miwa

Kanji Oishi

Atsushi Nozoe

Kazuo Kanetani

Tetsurou Matsumoto

Shoji Wada

Yoji Idei

Tetsu Udagawa

Yoshitaka Kinoshita

Kyoko Ishii

Tatsuyuki Ohta

Hiromi Tsukada

Yoshiaki Ouchi

Kazuo Mihashi

Manabu Ishimatsu

Toshitsugu Ueda

Yoshinobu Nakagome

Hiroaki Nambu

Masanori Odaka

Hisayuki Higuchi

Youji Idei

Toshikazu Tachibana

Akira Ide

Yoshiaki Sakurai

Kouichirou Noda

Shigenobu Kato

Kazuhiko Kajigaya

Takeshi Sakata

Masahiro Iwamura

Hugh Pryor McAdams

Kunio Uchiyama

Ikuro Masuda

Wah Kit Loh

Yoshifumi Kawamoto

Makoto Hanawa

Makoto Suzuki

Hiroyuki Miyazawa

Kazuhiko Sagara

Nobuo Tamba

Kyoichiro Asayama

Masayuki Ohayashi

Seigoh Yukutake

Toshiro Hiramoto

Adin E Hyslop

Kiyoo Ito

Kayoko Saito

Kenichi Ohata

Hiroaki Nanbu

Akihiro Tanba

Noriyuki Hamma

Hiromi Tukada

Mssashi Horiguchi

Ken'ichi Ohata

Yoshikasu Saito

Hideo Sunami

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed

Large-Capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.

Semiconductor device

There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banksthrough, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 &#x3bc;m. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.

Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase operational speed

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

System with meshed power and signal buses on cell array

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.

Semiconductor memory

Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

Semiconductor memory device

Growing community of inventors

Tokyo, Japan

Goro Kitsukawa