Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Goro Hayakawa

Yasuhiko Tsukikawa

Koji Tanaka

Takashi Itou

Susumu Tanida

Mitsunori Tsujino

Osamu Kuromiya

A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

Semiconductor integrated circuit having test circuit

A semiconductor integrated circuit includes: first and second counters activated upon receipt of a low level signal and outputting a signal with a period which is twice that of the signal input; first fuse circuits connected to first counters; and a second fuse circuit connected to second counter. First counters are inactivated when fuses included in first fuse circuits are disconnected, and second counter is activated when a fuse included in second fuse circuit is disconnected. Thus, the period of a signal for determining a refresh period can be efficiently adjusted. Here, the arrangement of first fuse circuits and a second fuse circuit can be converse.

Semiconductor integrated circuit capable of readily adjusting circuit characteristic

A refresh operation is started in response to activation of a refresh control signal. The refresh control circuit controls activation of a refresh control signal in accordance with a signal level of a row address decode enable signal in addition to signal levels of control signals activated in response to activation of signals /CAS and /RAS necessary for detecting the start of a CBR refresh operation. The row address decode enable signal is an internal control signal activated upon activation of a signal /RAS and maintained in an active state until signal /RAS is inactivated. As a result, the refresh control signal is not erroneously activated during normal operation even when a noise is caused to signal /RAS.

Semiconductor memory device preventing malfunction during refresh operation even when noise is superimposed on control signal

A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.

Semiconductor memory device having selection circuit for arbitrarily

A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

Dynamic semiconductor memory device that can control through current of

When a pad is connected to ground and a mode switching signal MHYP attains an L level, an integrated semiconductor device attains an FP mode. Following the transition of an internal column address strobe signal ZCASF and an internal write enable signal ZWEF to an L level, an NOR gate is opened to allow entry of internal data. When the pad is connected to a power supply potential and the mode selecting signal MHYP attains an H level, the integrated semiconductor device attains an EDO mode. The NOR gate is opened when the internal row address strobe signal ZRASF attains an L level, whereby the external data is entered. The writing operation in an EDO mode can be increased in speed.

Growing community of inventors

Hyogo, Japan

Goro Hayakawa