Cypress Semiconductor Corporation

Gorley L Lau

Ende Shan

Sam G Geha

Mira Ben-Tzur

Krishnaswamy Ramkumar

Dafna Beery

Chan-Lon Yang

Ivan Petrov Ivanov

Feng Dai

Anthony Chung

In one embodiment, a via structure includes a liner, a barrier layer over the liner, and an aluminum layer over the barrier layer. The barrier layer helps minimize reaction between the aluminum layer and the liner, thus helping minimize void formation in the via. The liner and the barrier layer may be deposited in-situ by ionized metal plasma (IMP) physical vapor deposition (PVD). In one embodiment, the liner comprises titanium, while the barrier layer comprises titanium nitride.

Aluminum-filled via structure with barrier layer

A method for fabricating a metallization structure is presented. The method preferably includes ion metal plasma depositing a wetting layer within a cavity defined in a dielectric layer. The wetting layer preferably includes titanium. The method preferably further includes sputter depositing a bulk metal layer within the cavity and upon the wetting layer. Sputter depositing of the bulk metal layer is preferably performed in a single deposition chamber at least until the cavity is substantially filled.

Method for forming a metallization structure in an integrated circuit

This invention relates to a method of forming a local interconnect and a semiconductor device comprising a local interconnect. The semiconductor device comprises:

Method of forming a low resistivity Ti-containing interconnect and semiconductor device comprising the same

In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Metal stack for local interconnect layer

The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

Low temperature metallization process

A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing &ldquo;bumps&rdquo; or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit

A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.

Method for forming void-free metallization in an integrated circuit

The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a low power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.

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Fremont, CA, United States of America

Gorley L Lau