Mcgill University

The Royal Institution for the Advancement of Learning / Mcgill University

Dft Microsystems, Inc.

Ciena Corporation

Gordon W Roberts

Mohamed M Hafed

Sadok Aouini

Clarence K L Tam

Sébastien Laberge

Jonathan Ikola Saari

Nate Quitoriano

James Forbes

Antonio H Chan

Geoffrey D Duerden

Naim Ben-Hamida

Mahdi Parvizi

David V Plant

Patanjali Kambhampati

Ramesh Abhari

Asanee Suntives

Bardia Pishdad

Nathan Smith

Mouna Safi-Harab

Mourad Oulmane

Mohammad Ali Bakhshian

David Robert Cameron Rolston

Ahmed Emara

Ming Yang

A X-bit Digital-to-Analog Converter (DAC) circuit includes an effective X/2-bit coarse DAC configured to produce a coarse bitstream (CBS) from a digital input DCusing an norder Sigma-Delta (&#x3a3;&#x394;) modulator, and to provide a coarse current source based on the CBS, wherein X is an even integer and n is an integer; an effective X/2-bit fine DAC configured to produce a fine bitstream (FBS) from a digital input DCusing a 1order &#x3a3;&#x394; modulator, and to provide a fine current source based on the FBS; and an output configured to form a voltage from the combination of the coarse current source and the fine current source.

Extremely-fine resolution sub-ranging current mode Digital-Analog-Converter using Sigma-Delta modulators

There is described herein methods and devices for high DC gain closed loop operation amplifiers exploiting cascaded low gain stages and a controller-based compensation circuit for stability.

Methods and devices relating to high gain amplifiers

Systems for analyte detection are disclosed. The system includes absorption channels positioned along a surface of an object. The absorption channels are configured to trap an analyte. The system further includes a sensor embedded in the object and configured to detect the presence of the analyte. The sensor includes a light source configured to transmit light and a detector configured to detect a change in an intensity of light transmitted by the light source. The sensor further includes a cable configured to connect the light source to the detector, wherein the cable comprises detection regions, and wherein the detection regions include a portion of the cable exposed to the analyte in the absorption channel.

Sensor systems and methods for analyte detection

Systems and methods for detecting target chemicals are disclosed. A system includes a chemical sensor configured to filter light. The chemical sensor includes a referencing arm configured to output light at a first intensity level and a sensing arm sensitive to a target chemical. The sensing arm is configured to output light at a second intensity level. A difference between the first intensity level and the second intensity level indicates a presence of the target chemical.

Systems for detecting target chemicals and methods for their preparation and use

Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. While driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.

Methods and devices relating to time-variable signal processing

A method and a circuit are provided for providing phase or frequency synthesis using sigma-delta modulation bit-stream techniques in which data is encoded utilizing sigma-delta modulation and then digital-to-time conversion (DTC) or digital-to-frequency conversion (DFC). In some embodiments this encoded data stream is further subjected to phase or frequency domain filtering, which in some embodiments is carried out by a higher-order phase-locked loop (PLL).

Phase/frequency synthesis using periodic sigma-delta modulated bit-stream techniques

The present invention relates to a method and system for providing an analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. A band-limited digital noise signal indicative of a Gaussian noise signal having a predetermined Gaussian probability distribution function is &#x3a3;&#x394; modulated generating a pulse-density modulated 1-bit sequence representing a Gaussian noise signal having a predetermined probability distribution function, bandwidth and center frequency. Using an analog low-pass filter the pulse-density modulated 1-bit sequence is then converted into a respective analog Gaussian noise signal having the predetermined probability distribution function, bandwidth and center frequency. The method and system are successfully employed in numerous applications such as in histogram testing and probabilistic digitization.

Generation of an analog Gaussian noise signal having predetermined characteristics

The present invention relates to a method and system for high-speed bandpass serial data communication. A driver receives at least one data signal and generates a bandpass data signal for transmission through a bandpass waveguide interconnect. The bandpass data signal is launched into the bandpass waveguide interconnect using a first adaptor and extracted therefrom after transmission using a second adaptor. A receiver connected to the second adaptor recovers the at least one data signal from the extracted bandpass data signal. A dispersion compensation circuit receives one of the at least one data signal and the bandpass data signal and information indicative of a phase response of the bandpass waveguide interconnect and dispersion compensates the one of the at least one data signal and the bandpass data signal by compensating the phase response of the bandpass waveguide interconnect.

High-speed bandpass serial data link

A method of providing an on-chip high-speed time domain digital analyzer for the characterization and analysis of signals within an integrated circuit is provided. The method involves processing the signal being characterized/analyzed in the digital domain irrespective of it's starting format. The approach performs a voltage-to-time conversion using predetermined voltage thresholds, applying a time amplification to the digital time information, measuring the amplified time difference between events and converting the amplified time difference as required by the characterization/analysis. The method allows the capture of very high-speed signals with high resolution without the requirements of complex and high-speed electronics. As such the on-chip high-speed time domain digital analyzer can function as an oscilloscope, pulse width analyzer, rise time analyzer and even logic analyzer. Further the method allows the capture and analysis of single and non-repetitive signal events unlike prior art approaches to time domain oscilloscopes.

Embedded time domain analyzer for high speed circuits

A multi-speed jittered signal generator () that generates a full-speed jittered signal () by scaling a low-speed jittered signal () using a frequency scaler (). The low-speed jittered signal is created by injecting a modulation signal () into a reference signal () using a jitter injector (). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system () for testing various circuitry, such as high-speed serializer/deserializer circuitry ().

System and method for generating a jittered test signal

A module (') containing an integrated testing system () that includes one or more measurement engines () tightly coupled with a compute engine (). The one or more measurement engines include at least one stimulus instrument () for exciting circuitry of a device-under-test () with one or more stimulus signals, and at least one measurement instrument () that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry () for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine () providing two-way communications between the integrated testing system automated testing equipment () and/or a dedicated user interface () residing on a host computer ().

System and method for testing integrated circuits

A method and an apparatus are provided for synchronizing clock signals in spatially distributed nodes in large, synchronous electronic, optical, optoelectronic or wireless systems, such as systems comprising arrays of microprocessors and memories, and telecommunication systems. The nodes comprise a master node and a plurality of slave nodes. The master node generates first and second identical pulse trains and propagates them to the slave nodes via a first and second propagation channels, respectively, so that a pair of pulses, one from each pulse train, arrive at each slave node substantially simultaneously, travelling in opposite directions. Each slave node generates a clock signal event in response to the substantially simultaneous arrival of each pair of pulses. The master node maintains the rate of the two pulse trains such that there are 'pN' pulses in each propagation channel at any time, where 'N' is the number of nodes and &#x201c;p&#x201d; is an integer. Adjustable delays are provided at each slave node, disposed in each propagation channel. When the pulses in the two channels do not arrive simultaneously, the slave node adjusts the delay units so as reduce differences in the arrival times of subsequent pairs of pulses. The delay units may comprise pre-delay units upstream of the detection point and post-delay unit downstream of the detection point, any increment in a pre-delay being compensated by an equal decrement in the post-delay in the same propagation channel.

Method and apparatus for distributed synchronous clocking

An integrated test core for mixed-signal circuits comprises a periodic waveform generator capable of generating arbitrary band-limited waveforms for excitation purposes and a waveform digitizer for extracting an arbitrary waveform from the test circuit's analog response signal. The digitized response may be tested and measured using DSP techniques. Preferably, the waveform generator and digitizer are synchronously controlled. The core is a nearly all digital implementation with the exception of a reconstruction filter (optional) for sending the test signal to the circuit under test (CUT) and the comparator for extracting the digitized waveform from the CUT's response. The periodic waveform generator may comprise a &#x3a3;&#x394; modulator and, optionally, a reconstruction filter between the modulator and CUT. The waveform digitizer may comprise a programmable reference voltage generator for providing a variable voltage reference signal, a comparator for generating a comparison signal from the CUT's analog response signal and the reference signal and means for controlling the reference voltage generator.

Integrated excitation/extraction system for test and measurement

A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point. The application of second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that a signal approximating the forcing parameter signal is caused at the output. A current measuring circuit adapted for providing a measure of the current at the external load suitable for use with a voltage generating circuit device is also provided.

Method and device for use in DC parametric tests

An efficient technique for generating accurate on-chip DC reference voltages is based on filtering a digital pulse modulated sequence in order to extract its average value encoding a DC level, A passive on-chip filter is used for simplicity with an all-digital modulator implementation. Modulation is proposed using pulse-width and preferably pulse-density modulation methods. The latter has the advantage of using a significantly smaller filter which translates into a smaller implementation and faster operational settling times. Many digital pulse modulation generators are proposed.

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Montreal, Canada

Gordon W Roberts