Lsi Logic Corporation

Lsi Corporation

Honeywell G.m.b.h.

Avago Technologies General IP (singapore) Pte. Ltd.

Gordon W Priebe

Richard John Stephani

Robin H Passow

David B Grover

Ankur Goel

Kevin R LeClair

Myron J Buer

Ronald D Isliefson

Carl W Swanson

Christopher D Browning

I Ross Mactaggart

Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.

Content addressable memory continuous error detection with interleave parity

An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.

Content addressable memory data clustering block architecture

A memory array is divided into multiple segments, each segment having one or more rows of bitcells. Each segment has control circuitry that controls whether the segment is in an active mode or a power-saving, sleep mode. The control circuitry ensures that a segment transitions from sleep mode to active mode before a row of the segment is accessed by driving a corresponding wordline high. The control circuitry also ensures that, at the end of a row access, the wordline is driven low before the corresponding segment is transitioned from active mode to sleep mode.

Segmented memory having power-saving mode

An apparatus comprising a memory array and a plurality of processing circuits. The memory array may be configured to store a plurality of data bits in a plurality of rows and a plurality of columns. A plurality of data words may be stored in a respective plurality of the columns. The plurality of processing circuits may each be configured to compare (i) a test bit of a plurality of bits of an input data word with (ii) a test bit of one of the plurality of columns to determine a match. The compare may occur on a first clock cycle of an input clock signal. Each of the plurality of processing circuits may be configured to power down a respective column of the memory array if the test bit of the input data word does not match the test bit of the column.

Low power SRAM based content addressable memory

A single ended bit line sensor includes a single ended bit line input, a sensor output, an inverting amplifier, a non-inverting amplifier and a differential amplifier. The inverting amplifier is coupled to the single ended bit line input and has a first voltage output. The noninverting amplifier is coupled to the single ended bit line input and has a second voltage output. The differential amplifier has first and second amplifier inputs coupled to the first and second voltage outputs, respectively, and has an amplifier output coupled to the sensor output.

High speed single ended bit line sense amplifier

A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines. However, if more than one hit line is asserted, the combined incremental change of voltage due to activation of two or more pull-up and pull-down devices is greater than the maximum voltage differential between the bit line signals asserted by the buffers, causing the bit line differential voltage to reverse polarity. The differential comparator detects the reversal of polarity of the bit line differential voltage and asserts an error signal. The multiple detection circuit further includes a transmission gate, which selectively equalizes charge on the bit lines, and isolation devices, which provide level shifting, prior to detection by the differential amplifier to thereby increase the speed of detection.

High speed method and apparatus for detecting assertion of multiple

A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential amplifier. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line by an incremental amount, thereby decreasing the bit line differential. The differential amplifier switches to indicate an error when the polarity of the differential voltage between the bit lines is reversed relative to the normal state. Any given single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage of the bit lines. However, if more than one hit line is asserted, then both bit lines are dominated by the activated complementary pull-up and pull-down devices, respectively, causing the bit line differential voltage to reverse polarity. In effect, the combined incremental change of voltage due to activation of two or more pull-up and pull-down devices is greater than the maximum voltage differential between the bit line signals asserted by the buffers. The differential error amplifier detects the reversal of polarity of the bit line differential voltage and asserts an error signal.

Method and apparatus for detecting assertion of multiple signals

A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit. If the data bit supports the default state, then the sense amplifier switches to the default state. However, if the data bit supports the first state, the sense amplifier quickly responds and slews back to the first state. In this manner, either logic state is achieved very quickly. Preferably, an invertor is coupled to the sense amplifier having an input switch-point set to favor the default logic state.

Fast memory sense system

A word line decoder gate including a plurality of parallel-coupled devices coupled to a common node for receiving and decoding an address upon assertion of a clock signal, where each parallel device receives a corresponding address signal or its inverted counterpart depending upon the particular address being decoded. A precharge device is coupled to the common node for keeping it at a first voltage level until the clock signal is asserted, and two series coupled charge devices are coupled between a source voltage and the common node, which charge devices attempt to charge the common node to a second voltage level during a time period while the clock signal is asserted and a delayed clock signal remains deasserted. A delay device receives the clock signal and asserts the delayed clock signal. However, any one or more of the parallel devices, if activated, provides a current path from said common node to override the two charge devices to keep the common node substantially at the first voltage level. Since decoding is performed in parallel, the present invention is easily extendible to as many address inputs as desired without any loss in performance. In the preferred embodiment, the parallel-coupled devices are discharge devices for keeping the common node discharged. Also in the preferred embodiment, a charge sustaining circuit is preferably coupled between the common node and the source voltage for reducing the effects of stray capacitance.

Fast word line decoder for memory devices

A self-timed memory control system including a dummy row and column of memory cells along adjacent edges of a core memory array. Control logic receives an external clock signal and initiates address decoding, and also asserts a sense enable signal for activating the sense amplifiers. A dummy driver receives the enable signal and asserts a select signal on a dummy select line, which causes a memory access to occur in the dummy portion simultaneously with each access of the core memory array. A fixed memory cell in the dummy path always asserts a logic zero to a dummy sense amplifier, which senses the logic zero and respondingly asserts a timing signal. The dummy sense amplifier is biased with a voltage offset to favor a logic one, so that the timing signal is preferably delayed until after the output data of the core memory array has stabilized. The control logic detects the assertion of the timing signal and respondingly latches the output data, and the control logic also shuts down the sense amplifiers to prevent further power drain. In this manner, the output data is latched and the sense amplifiers are disabled as soon as possible to conserve energy but within a safe timing margin to assure that valid data is properly latched. A biased inverter is preferably added for further timing margin. The sense amplifiers preferably include an input level-shifter stage for proper operation at low voltage levels.

Method and apparatus for a low power self-timed memory control system

A test system for determination of the integrity of interconnections between integrated circuits based on test circuit portions provided in such integrated circuits which are subject to signals from the inputs that might vary in value because of faulty interconnections. The values on such inputs are set, in the absence of input signals reaching them, by switchable resistances in the corresponding test circuit portions each of which can couple a predetermined signal value to a corresponding input, but which can also be overridden by signals supplied to that input across the corresponding interconnection from a source thereof.

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Champlin, MN, United States of America

Gordon W Priebe