International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Gordon Taylor Davis

Malcolm Scott Ware

Clark Debs Jeffries

Marco C Heddes

Jean Louis Calvignac

Jeffrey Haskell Derby

Hua Ye

Dongming Hwang

Claude Basso

Youssef Abdelilah

Ajay Dholakia

Everett Arthur Corl, Jr

Piyush Chunilal Patel

Baiju Dhirajlal Mandalia

Fredy Daniel Neeser

Fabrice Jean Verplanken

Evangelos Stavros Eleftheriou

Michael Steven Siegel

Ravinder Kumar Sabhikhi

Ross Boyd Leavens

Brian Mitchell Bass

Sumedh Wasudeo Sathaye

Chih-Jen Chang

Mark Anthony Rinaldi

Steven Richard Perrin

Grayson Warren Randall

Colin Beaton Verrilli

Brett Olsson

Eric Francis Robinson

Richard William Doing

Sonia Kiang Rovner

John C Sinibaldi

John David Jabusch

Jeffrey Richard Summers

M V V Anil Krishna

Sedat Oelcer

Andreas Guenther Herkersdorf

Laurence Victor Marks

Charles Robert Young

Philippe Damon

Srinivasan Ramani

Ken Van Vu

Cloyd Stanley McIlvaine

William R Robinson, Jr

Dana Lynn Blair

Sebastian Theodore Ventrone

Bartholomew Blaner

Harm Peter Hofstee

Natarajan Vaidhyanathan

Clarence Rosser Ogilvie

Jan Van Lunteren

Hans-Werner Tast

Anthony Matteo Gallo

Michael Raymond Trombley

Anil Krishna

James Johnson Allen, Jr

Steven Kenneth Jenkins

Thomas Basilio Genduso

Robert Brian Likovich, Jr

Lawrence P Andrews

Joseph Franklin Garvey

Paul C Stabler

Alfred A Stricker

Gordon Bernard Bell

Rama Mohan Yedavalli

William M Zevin

Llewellyn Bradley Marshall, Iv

Jitesh Ramachandran Nair

Robert John Schule

Kartik Sudeep

Robert E Landa

Victoria Sue Thio

Jan W Van Den Berg

Lawrence P Remsen

Steve Woolet

Hiroshi Takada

Santiago A Leon

Youseff Abdelilah

Thomas Andrew Sartorius

Jeffrey Todd Bridges

Kenneth James Barker

Robert J Devins

John J Reilly

Jeffrey Powers Bradford

Harold F Kossman

David Curtis Van Voorhis

Wolfgang F Mueller

Patrick K Kam

Robert W Todd

Robert A Magee

Judith Marie Linger

Oscar E Ortega

Andre Byungyup Minn

Angelo S Gasparri

Charles Bruce Dillon

Challis L Purrington, Sr

Edward Earl Harbour

Willie James Johnson

Leo A Sharp, Jr

James L Patrick, Jr

A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

Prefetching with multiple processors and threads via a coherency bus

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Structure for supporting simultaneous storage of trace and standard cache lines

In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.

Methods and apparatus for dynamically switching processor mode

Effective prefetching with multiple processors and threads

Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a patricia tree having leaf keys and pattern search control blocks containing a prefix and either an end-of-trail leaf or a pointer to another of the pattern search control blocks, by placing each of the prefixes in a tree prefix table; searching for a key in the tree; searching for the key in the prefix table if the tree searching does not find the key in the tree; confirming that the key is deleted if the key is not found in the prefix table; deleting the key from one of the pattern search control blocks; and collapsing the patricia tree by eliminating the left most pattern search control block from the patricia tree if the patricia tree searching finds the key.

Deleting leaves in tree table structures

The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

Retro flow control for arriving traffic in computer networks

A method for increasing the capacity of a connection table in a firewall accelerator by means of mapping packets in one session with some common security actions into one table entry. For each of five Network Address Translation (NAT) configurations, a hash function is specified. The hash function takes into account which of four possible arrival types a packet at a firewall accelerator may have. When different arrival types of packets in the same session are processed, two or more arrival types may have the same hash value.

Efficiently hashing packet keys into a firewall connection table

Computers are caused to provide a hash table wherein each entry is associated with a binary key and indexed by a selected portion of a hash value of the associated key, and points to a data structure location for storing non-selected portions of, or the entire hash value of, the binary key, and action data corresponding to the value of the binary key. Content addressable memory entries store a binary key, or a value unique to it, and an association to a corresponding action. Pointers to the data structure use selected portions of binary key hash values as an index when not selected portions of hash values of other binary keys, and associations are established between CAM entry and associated data structure locations when selected portions of the hash values of the binary keys are the same as selected portions of hash values of one or more other binary keys.

Lookups by collisionless direct tables and CAMS

The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, an implementation is provided wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Memory-centric page table walker

The classification system of a network device includes a cache in which a mapping between predefined characteristics of TCP/IP packets and associated actions are stored in response to the first 'Frequent Flyer' packet in of a session. Selected characteristics from subsequent received packets of that session are correlated with the predefined characteristics and the stored actions are applied to the received packets if the selected characteristics and the predefined characteristics match, thus reducing the processing required for subsequent packets. The packets selected for caching may be data packets. For mismatched characteristics, the full packet search of the classification system is used to determine the action to apply to the received packet.

Caching lookups based upon TCP traffic flow characteristics

A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

Controller for multiple instruction thread processors

Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.

System for defining data mappings between data structures

A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Apparatus and method for using branch prediction heuristics for determination of trace formation readiness

A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.

Structure for a memory-centric page table walker

A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

Network processor with single interface supporting tree search engine and CAM

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Chapel Hill, NC, United States of America

Gordon Taylor Davis