Freescale Semiconductor,inc.

Qualcomm Incorporated

Gordon P Lee

Jiang-kai Zuo

Todd Robert Sutton

Robert W Baird

Won Gi Min

Marko Harry Koski

Michael Priel

Christopher K Y Chun

Cor Voorwinden

Lalan Jee Mishra

Christopher K Chun

Brandt Braswell

Keith Alan Bowman

Matthew Levi Severson

Wayne W Ballantyne

Chiew-Guan Tan

Christopher Kong Yee Chun

Dipti Ranjan Pal

Cheong Kun

Bharat Kumar Rangarajan

Vijayakumar Ashok Dibbad

Ravi Jenkal

Eric B Zeisel

Youssef H Atris

Darren V Weninger

Narendra Singh Mehta

Anish Muttreja

Jennifer A Hagstrom

Zdravko Lukic

Scott A Tassi

Edgar Marti-Arbona

Hector Freires Corleto

Brian E Chang

Christopher Ky Chun

Siegfried W Breitmeier

Adrian M Stenzel

A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

Methods and apparatuses for extended current limit for power regulation

In controlling power in a portable computing device ('PCD'), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.

Power controller communication latency mitigation

The present disclosure describes aspects of voltage settling detection for switching regulators. In some aspects, an integrated circuit for controlling a switching regulator includes a modulator having an output coupled to switch drive circuitry of the switching regulator. A digital-to-analog converter (DAC) has a first output coupled to an input of the modulator and a second output configured to indicate when a digital-to-analog conversion is complete. A voltage settling detector is configured to receive, from the second output of DAC, an indication that the digital-to-analog conversion is complete and detect a signal transition at the output of the modulator. Based on the indication and the signal transition, the voltage settling detector can provide a status indication for the switching regulator. By so doing, the voltage settling detector may indicate that an output voltage of the switching regulator is proximate a target output voltage level set by the DAC.

Voltage settling detection for switching regulators

System, methods, and apparatus are described that facilitate signaling between devices over a single bi-directional line. In an example, the apparatus couples a first device to a second device via a single bi-directional line, indicates initiation of a first action, initiated at the first device, by sending a first single transition on the single bi-directional line from the first device to the second device, and indicates initiation of a second action, initiated at the second device, by sending a second single transition on the single bi-directional line from the second device to the first device. In another example, a first device initiates a first action, indicates initiation of the first action by generating a first event on a single bi-directional line, and receives an indication of a second action initiated at a second device by observing a second event on the single bi-directional line.

Single line PMIC-host low-level control interface

Disclosed is a voltage regulator circuit configured to selectively operate the voltage regulator circuit in a first mode of operation and a second mode of operation. The voltage regulator can change operation of the voltage regulator circuit between the first mode of operation to the second mode of operation in response to a change in a sensed load condition of the voltage regulator circuit. The voltage regulator can change operation from the second mode of operation to the first mode of operation in response to the sensed load condition changing from the second load condition to the first load condition, but only when the sensed load condition has not changed in a given direction between the first load condition and the second load condition for at least a predetermined period of time T.

Voltage regulator having auto mode optimized for load profiles

A method, an apparatus, and a computer program product for booting the apparatus with a low-energy battery are provided. In a first configuration, the apparatus monitors a level of the battery while the battery is charging. The apparatus attempts a boot of the apparatus when the level is greater than or equal to a dynamic boot threshold. The apparatus increases the dynamic boot threshold when the boot is unsuccessful and repeating the monitoring and the attempting based on the increased dynamic boot threshold. In a second configuration, the apparatus detects a connection to an external power source. The apparatus attempts a boot using an FLCB protocol that is based upon power drawn directly from the external power source upon detecting the connection to the external power source. The apparatus attempts the boot as part of an ATC protocol when the boot using the FLCB protocol is unsuccessful.

Booting a mobile electronic device with a low battery based on a dynamic boot threshold

A method and apparatus for extending the driving capacity of a power management device are provided. The method involves determining an energy requirement for the operation of a power management device. Next, the method compares the energy requirement for the operation of a power management device with a capability of a first power device. If the energy requirement is greater than the energy requirement of the first power device, the energy is switched to a second power device of higher capacity. The apparatus includes: a first power device; a second power device connected in parallel to the first power device; a first inductor connected to the first power device and a capacitor connected to the first inductor; and a second inductor connected to a second power device and a capacitor connected to the second inductor.

Parallel arrangement of asynchronous buck converters for advanced power capability

A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method further includes monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. Also disclosed is a device for implementing the method of media access control.

Device and method for media access control

A switcher system or circuit and corresponding methods provide dynamic voltage scaling. One embodiment of an apparatus includes: a switcher controller configured to monitor a signal from a processor for a first state, determine a time that the signal is in the first state, and provide an adjustment signal based on the time, and a power supply coupled to the adjustment signal and configured to provide a variable supply voltage to the processor core, the variable supply voltage controlled by the adjustment signal after the determining a time.

Dynamic voltage scaling interface

A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.

Method and device for frame synchronization

An antifuse element () includes a substrate material () having an active area () formed in an upper surface, a gate electrode () having at least a portion positioned above the active area (), and a gate oxide layer () disposed between the gate electrode () and the active area (). The gate oxide layer () includes one of a gate oxide dip () or a gate oxide undercut (). During operation a voltage applied between the gate electrode () and the active area () creates a current path through the gate oxide layer () and a rupture of the gate oxide layer () in a rupture region (). The rupture region () is defined by the oxide structure and the gate oxide dip () or the gate oxide undercut ().

Antifuse elements

An antifuse element () and method of fabricating the antifuse element, including a substrate material () having an active area () formed in an upper surface, a gate electrode () having at least a portion positioned above the active area (), and a gate oxide layer () disposed between the gate electrode () and the active area (). The gate oxide layer () including the fabrication of one of a gate oxide dip () or a gate oxide undercut (). During operation a voltage applied between the gate electrode () and the active area () creates a current path through the gate oxide layer () and a rupture of the gate oxide layer () in a rupture region (). The rupture region () defined by the oxide structure and the gate oxide dip () or the gate oxide undercut ().

Antifuse element and method of manufacture

An antifuse element () having end corners () of a gate electrode () positioned directly above an active area () or bottom electrode. The minimum programming voltage between the gate electrode () and the active area () creates a current path through an insulating layer () positioned therebetween. The high electric field created at the end corners () of the gate electrode () results in a breakdown and rupture of the insulating layer () at points directly beneath the end corners (). This localization of the insulating layer () at the corners () provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements () when integrated into an array () provide for increased packing density. The array is fabricated to include multiple active areas () for individual antifuse element () programming or a common active area () for multi-element programming.

Antifuse element and electrically redundant antifuse array for controlled rupture location

A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.

Audio modulated light system for personal electronic devices

Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.

Growing community of inventors

Mesa, AZ, United States of America

Gordon P Lee