National Semiconductor Corporation

Gordon L Mortensen

Pavel Poplevine

James Thomas Doyle

Wai Cheong Chan

Hsing-Chien Roy Liu

Murali Krishna Varadarajula

Neal L Horovitz

The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

Closed-loop, supply-adjusted ROM memory circuit

Closed-loop, supply-adjusted RAM memory circuit

A circuit is provided that reduces the electromagnetic emissions from an integrated circuit. The circuit includes the resistive portion of an intrinsic low pass filter network and a means for modulating the resistance in response to switching of the integrated circuit nucleus logic elements. The resistance is increased before the nucleus logic elements switch and is gradually decreased upon completion of all switching of the nucleus logic elements. A portion of the transient switching pulse waveform, normally provided by the external power supply, is instead provided by the intrinsic nucleus capacitance associated with the nucleus logic. In particular the high frequency components are sourced by the intrinsic nucleus capacitance. The amplitude and the rise time of the transient switching pulse is thereby reduced. Further reduction in electromagnetic emission is provided by modified output buffers where transient switching waveforms are reduced by current limiting the output switching transistors and providing initial transient current from the intrinsic capacitance associated with the output buffer.

Integrated circuit having reduced electromagnetic emissions an

An electrostatic discharge protection circuit having a non-lightly doped drain MOS device for protecting other lightly doped drain devices on an integrated circuit, and a method of concurrently fabricating both the non lightly doped and lightly doped devices on the substrate of the integrated circuit using substantially the same set of processing steps.

Electrostatic discharge protection device and a method for

A brownout reset generator includes a presettable counter and a reset controller consisting of a plurality of logic gates coupled to receive a brownout signal representing a power brownout condition or power assertion (i.e. power-up) and a clock signal, and to generate a brownout reset in response to and of selectively longer duration than the brownout signal. Following the leading edge of the brownout signal (i.e. initiation of the brownout condition), the counter is preset to a selected value and remains preset for the duration of the brownout signal. Following the trailing edge of the brownout signal (i.e. termination of the brownout condition), the counter begins counting clock pulses. The counter outputs a timing pulse after a selected number of clock pulses representing a predetermined time interval have been counted. The reset generator provides a brownout reset having a leading edge following and corresponding to the leading edge of the brownout signal and a trailing edge following and corresponding to the leading edge of the timing pulse. Thus, the brownout reset causes its user circuit (e.g. microprocessor) to remain in a brownout reset mode until after the predetermined time interval has passed following termination of the brownout condition. This allows sufficient time for the user circuit's operating parameters to stabilize (e.g. crystal clock signal) or initialize (e.g. internal registers and address pointers) properly prior to resuming operation following termination of the brownout condition.

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San Jose, CA, United States of America

Gordon L Mortensen