Intel Corporation

Medimmune Limited

Theraclone Sciences, Inc.

Gordon King

Jennifer L Mitcham

Alaa R Alameldeen

Kenneth H Grabstein

Ole Olsen

Matthew Moyle

William Brady

Zhe Wang

Yi Zou

Natalie Winblade Nairn

Thomas C Cox

Andrea Wang

Kurt David Shanebeck

Paul Heffner Slagle

Kenneth Christopher Thornton

Michael Peter Vanbrunt

Hengyu Xu

Andres G Grandea

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

Direct mapped caching scheme for a memory side cache that exhibits associativity in response to blocking from pinning

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Portland, OR, United States of America

Gordon King