International Business Machines Corporation

Motorola Corporation

Gordon J Robbins

Madhavan Swaminathan

Michael F McAllister

Keshav B Prasad

James A McDonald

Eric D Perfecto

Chandrika Prasad

George E White

Sudipta Kumar Ray

Robert Charles Dockerty

Ciro Neal Ramirez

Ronald Maurice Fraga

Edward B Eichelberger

Robert R Shaw

Antonio R Gallo

Gregory Martine Wilkins

David R Bearden

Carlos Munoz-Bustamante

Joel C Leininger

James W Davis

Donald Norman Senzig

James J McDonough

Charles Levern Reynolds, Jr

The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus. For high performance operation where higher cost for higher bandwidth is justified, the bidirectional bus is gated to be a device output only bus and the alternate device input bus is gated to the processor input bus creating a true uni-directional bus structure. The bus enable line is wired to the appropriated stated depending on the wired microprocessor bus structure.

Microprocessor bus structure

Structure and method for reinforcing a solder column grid array attachment of a ceramic or the like substrate to a printed circuit board, the reinforcement providing support for a heat sink which is bonded or affixed by pressure to a structural element of the substrate. In one form, the invention involves the concurrent formation of materially larger solder columns along the perimeter of the substrate in conjunction with the array of thin electrically interconnecting solder columns on the substrate. The reinforcing and electrical signal columns are thereafter aligned and attached by solder reflow to a corresponding pattern of pads on the printed circuit board. The heat sink is thermally connected to a structural element of the substrate by bonding or mechanical compression. Stresses in the solder columns caused by heat sink compressive forces or vibration induced flexing are materially decreased without adding complex or unique manufacturing operations.

Column grid array substrate attachment with heat sink stress relief

A multi-processor system and methodology optimize overhead costs associated with manufacturing large integrated circuit devices having multiple data processors and processing elements thereon by effectively disabling processing elements that are not functional. Disabling the processing elements is performed through segmented power distribution on an integrated circuit first-level package or by providing inhibit signals in pre-selected logic states based on the functionality of the multi-processing system. The functionality of the multiprocessing system is determined during an initial testing procedure, including wafer-level testing.

Design and methodology for manufacturing data processing systems having

A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Minimal capture pads applied to ceramic vias in ceramic substrates

A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Method of constructing an integrated circuit memory

Supporting structure for a ball grid array surface mounted integrated circuit device composed of support solder formed at selective corner locations on the ball grid array surface of the integrated circuit device. In one form, L-shaped patterns of high melting temperature solder are formed along the axes defined by the ball grid array and are characterized in that cross sections of the L-shaped pattern match that of the solder balls along one axis, and represent a continuum of solder between solder ball locations along the other axis. Support solder can be added where necessary to provide both structural reinforcement and thermal conduction. Control of the cross section of the support solder ensures that surface tension effects of the molten low temperature reflow solder used to connect the integrated circuit device does not materially change the final relative spacing between the integrated circuit device balls and the underlying printed circuit board contacts.

Structurally reinforced ball grid array semiconductor package and systems

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Method for repairing defective electrical connections on multi-layer

High density memory structure

A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

Thin-film wiring layout for a non-planar thin-film structure

A waveguide structure is directly extruded onto a surface from a nozzle placed a predetermined distance above the surface and which is moved relative to the surface, preferably by means of a translation table. The predetermined distance is preferably maintained constant and the speed of relative motion regulated to achieve a uniform degree of molecular orientation within the extruded material, thus maintaining a sufficiently uniform refractive index along the axis of the waveguide. Partitions within the nozzle allow the formation of a layered waveguide or the simultaneous formation of concentric cladding or protective layers. The waveguides are advantageously formed as a curtain which is later patterned, by direct writing on the surface or between chips mounted on an electronic module.

Extrusion of polymer waveguides onto surfaces

Disclosed is an optical signal distribution system. The system comprises an electronic substrate, at least one optical component and at least one optical waveguide on but distinct from the electronic substrate for carrying an optical signal to or from the optical component.

Optical signal distribution system

A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A 'merged' L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.

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Wappingers Falls, NY, United States of America

Gordon J Robbins