Xilinx, Inc.

Agilent Technologies, Inc.

Gordon I Old

Richard Lewis Walke

Ben J Jones

Andrew M Whyte

Zahid Khan

Ming Ruan

Jonathan Castelli

Justin A Fritz

An apparatus and method for determining an alignment of a codeword is disclosed. A data stream may be received, and a cumulative syndrome value determined. The cumulative syndrome value may be based on error correction and data scrambling operations performed on the data stream. If the cumulative syndrome value matches a predetermined cumulative syndrome value, then alignment of the codeword with respect to the data stream is determined.

Method and apparatus for codeword alignment

Embodiments described herein provide a code generation mechanism (FIG.) in a Polar encoder (FIG.) to determine a bit type (FIG.) corresponding to each coded bit in the Polar code before sending the data bits for encoding (FIG.). For example, each bit in the Polar code is determined to have a bit type of a frozen bit, parity bit, an information bit, or a cyclic redundancy check (CRC) bit based at least on the respective reliability index of the bit from a pre-computed reliability index lookup table (FIG.A,). In this way, the bit type determination can be completed in one loop by iterating the list of entries in the pre-computed reliability index lookup table.

System and method for determining bit types for polar encoding and decoding

A circuit for implementing a polar decoder is described. The circuit includes a log-likelihood ratio processing circuit. A path metric update circuit is coupled to receive log-likelihood values for decoded bits from the log-likelihood ratio processing circuit, wherein the path metric circuit generates path metric values for the decoded bits. A partial sum calculation circuit is coupled to receive the path metrics; and a sort and cull circuit is coupled to receive a list of child path, wherein the sort and cull circuit eliminates invalid paths from the list of child paths. A method of implementing a polar decoder is also described.

Circuit for and method of implementing a polar decoder

A decoder circuit includes an input configured to receive an encoded message, and a decoding loop circuit including first and second memories, an update circuit, and a sort circuit. The decoding loop circuit is configured to perform list decoding to the encoded message by successively decoding a plurality of bits of a first codeword of the encoded message in a plurality of decoding loops respectively; and provide, to an output, a decoded message. In each decoding loop, the update circuit is configured to receive, from the first memory, parent path values, and provide, to a second memory, child path values based on the parent path values. The sort circuit is configured to receive, from the second memory, the child path values; and provide, to the first memory, surviving child path values based on the child path values.

System and method for successive cancellation list decoding of polar codes

An apparatus for an exponential function for a half-precision floating-point format for an exponent x includes a denormalizer for receiving sign, exponent and significand bits for conversion of significant bits to a fixed-point format for a signed fixed-point representation. A splicer receives the signed fixed-point representation to output first, second and third splices. A first lookup table receives the first splice for accessing a floating-point exponent and a floating-point mantissa. A second lookup table receives the second splice for accessing a fixed-point exponent value. A first multiplier receives the fixed-point exponent value and the third splice to provide a first multiplication result. An adder receives the fixed-point exponent value and the first multiplication result to provide a sum. A second multiplier receives the floating-point mantissa and the sum to provide a second multiplication result. A combination of the floating-point exponent and the second multiplication result is a floating-point value.

Apparatus and method for an exponential operator for a half-precision floating-point format

Apparatus and method relates generally to data processing kernel. In such an apparatus, a datapath pipeline is configured to process datasets interlaced with respect to one another for multiple passes through a loop with conditional or data dependent decision points. A queue manager is configured with control circuitry sets to provide an instruction interface to the datapath pipeline. Each of the control circuitry sets includes: a first buffer and a second buffer each configured to buffer tokens for correspondence with the datasets. Each of the control circuitry sets further includes: an arbiter configured to decouple the conditional or data dependent decision points from the datapath pipeline to selectively provide access of the first buffer or the second buffer to the datapath functions. Memory is configured to provide access to and storage of the datasets to the datapath pipeline.

Linear block code decoding

Apparatuses and methods generally relating to a sort system, such as may be used in a data processing kernel, for list decoding of a Polar codeword are described. In one such sort system, a sorter circuit is configured to receive and sort path metrics for coded bits of the Polar codeword. The path metrics are obtained from log-likelihood ratios associated with the coded bits. A limiter circuit is configured to cull the sorted path metrics to provide a list having a subset of the path metrics to limit output paths of a list decoder. A normalizer circuit is configured to subtract a path metric of the path metrics or a threshold metric representing a minimum metric respectively from entries in the list to provide normalized path metrics to decode the Polar codeword.

Sort system including normalization

Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select.

Log-likelihood ratio processing for linear block code decoding

An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

Pipelined phase accumulator

A multiplier circuit and method multiply a signed value by a constant. The signed value received at an input port is separable into two or more splices. A first splice is a most significant one of the splices, and a second splice is another one of the splices. One or more memories provide respective partial products for the splices, and these memories include a shared memory. The shared memory provides the respective partial products for the first and second splices from storage locations in the shared memory. The storage locations that are readable to provide the respective partial product for the second splice are a subset of the storage locations that are readable to provide the respective partial product for the first splice. An addition circuit sums the respective partial products for the splices.

Circuit and method for multiplying a signed value by a constant

Radix-based division is described. A dividend operand and a divisor operand are obtained. An estimate that is a reciprocal of the divisor operand is obtained. For a prescaling mode, a prescaling iteration is performed which includes: multiplying the divisor operand with the estimate to provide a prescaled divisor; apportioning the dividend operand into portions from most significant to least significant; providing the estimate to iteration blocks ordered from highest to lowest; providing the most significant to the least significant of the portions of the dividend operand respectively to the highest to the lowest of the iteration blocks; respectively multiplying the portions of the dividend operand with the estimate to provide first partial products; and parsing most significant residue portions and least significant residue portions as associated with order of the iteration blocks from the first partial products.

Iterative stage as dividend operand prescaler for fixed-radix division

A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Phase accumulation

Phase-to-sinusoid conversion and method for direct digital synthesis are described. At least one quadrant of values for a sinusoidal signal are real-to-finite bit resolution mapped to provide preconditioned values which are on average shifted down by half of a LSB position. The at least one quadrant of preconditioned values are stored in a lookup table. MSBs of a phase-accumulated signal are used as an address for accessing from the lookup table a sinusoid value. At least a logicis added as an LSB to an interim output associated with the sinusoid value to provide an adjusted sinusoid value having a bit width greater than that of the sinusoid value to provide a digitally synthesized sinusoidal value.

Phase-to-sinusoid conversion

In the field of optical communications, the need to remove jitter from a Synchronous Digital Hierarchy (SDH) or Synchronous Optical NETwork (SONET) datastream is recognized. Consequently, the present invention provides a First-In-First-Out (FIFO) buffer having a read-out clock frequency that is controlled in response to a depth error of the FIFO buffer. The control of the read-out clock frequency is achieved by a hardware control loop coupled to the FIFO buffer. The period of the control loop is a product of the frequency at which the depth error of the FIFO buffer is acquired and another factor. The another factor is the number of states of logic employed by the control loop raised to an integer power.

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Edinburgh, United Kingdom

Gordon I Old