Lattice Semiconductor Corporation

Gordon Hands

Satwant Singh

Wei Han

Fulong Zhang

Ming Hui Ding

Sreepada Hegade

Ravindar Mohan Lall

Joel Coplen

Ravindar Lail

Joel Copien

Ravindar Lall

Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

Fast boot systems and methods for programmable logic devices

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San Jose, CA, United States of America

Gordon Hands