Motorola Corporation

Freescale Semiconductor,inc.

Gordon H Allen

Kenneth I Ray

Byron G Bynum

David B Harnishfeger

Robert A Neidorff

Bryan Quinones

Peter J Bills

According to one embodiment, an integrated fault detector circuit is used to detect one or more of the open circuit and short circuit of a load connected to an integrated circuit power MOSFET driver by directly detecting the level of current flowing in a floating current source.

Integrated fault detector circuit

A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.

Voltage translator circuit

A circuit for producing a pair of output pulses for each cycle of differentially applied input pulses includes a pair of input transistors to which the differential input pulses are applied and a pair of output transistors the collectors of which are connected to an output of the pulse doubling circuit and the bases of which are respectively coupled to the emitters of a corresponding input transistor. A pair of delay circuits are provided coupled respectively from one of the input transistors to the base of the opposite output transistor. The output transistors are responsive to the respective input transistor being rendered conductive while the other input transistor is rendered non-conductive for causing the output voltage to change from a first level to a second level while the one delay circuit is responsive to the other input transistor turning off for turning the respective output transistor to turn off a predetermined time thereafter thereby causing the output voltage to change from the second level to the first level.

Pulse doubler circuit with complementary pulse inputs

A feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state. Additionally, if the push-pull output stage is incorporated within a three state gate or the like, which gate shares a common bus with other like three state gates, the feedback circuit inhibits loading of the bus whenever the three state gate is operated in a three state mode or is powered down as the other gates are active and are rapidly transitioned between low and high output states. The feedback circuit provides a low impedance path at the input of the lower transistor amplifier of the push-pull driver output stage to shunt transient currents harmlessly away from the base thereof to prevent the transient currents from turning on the lower transistor amplifier.

Miller capacitance effect eliminator for use with a push-pull amplifier

A 'H' switching circuit for providing current drive to a load coupled between first and second outputs thereof comprising first and second paired switching transistor circuits each including an upper transistor that is cross-coupled at the first and second outputs to a respective paired lower transistor. The respective pairs of switching transistors are alternately rendered conductive whereby the polarity of the load current drive may be reversed. First and second transistors are provided with each being coupled respectively between a lower transistor of one of the paired switching transistor circuits and the upper transistors of the other one of the paired switching transistor circuits for severely limiting current spikes that otherwise occur during switching at the outputs of the switching circuit.

Switch circuit having improved switching characteristics

A TTL to high level translator having improved high state current drive includes a push-pull output stage and a lateral PNP transistor for supplying current drive when the translator is in a high state. The output stage consists of a pair of Darlington connected transistors comprising an upper amplifier and a lower transistor amplifier connected in series with the upper amplifier. A current transient suppressor circuit circuit is coupled with the bases of the pair of Darlington connected transistors for inhibiting power supply current spikes as the upper and lower amplifiers are alternately turned on and off in response to the TTL logic signal switching between upper and lower level states.

Low level logic to high level logic translator having improved high

A circuit is disclosed for providing multiple output currents having magnitudes which are of a predetermined ratio of the magnitude of an input current. The circuit includes an input transistor and at least two output transistors. The emitters and bases of the input and two output transistors are connected in common with the emitters thereof being connected to a terminal at which is supplied a source of operating potential. The collectors are respectively coupled to individual utilization means. First and second additional transistors are provided having symmetrical structures with the bases thereof being connected to the bases of the output transistors and their emitters connected to the collector of the first output transistor. The collectors of the two output transistors are connected respectively to the collector of the input transistor and the collector of the second output transistor whereby all of any saturation current produced by the first output transistor becoming saturated is equally conducted between the two additional transistors to maintain the ratio of input and output currents.

Current source having saturation protection

A TTL transparent latch circuit includes an input transistor having a base coupled to an input data signal and having emitter and collector terminals coupled respectively to the emitter and collector terminals of a latching transistor. A latch disabling signal is also coupled to the base of the input transistor which, when high, places the circuit in a transparent mode. An inverting gate inverts a latch enabling signal to form the latch disabling signal. The emitter of an additional transistor is coupled to the enabling signal, and the collector of the additional transistor is coupled to the base of the latching transistor. The base of the additional transistor is coupled to a source of supply voltage and to the output of the inverting gate. In this manner, the latching transistor is turned off simultaneously with turning the input transistor on.

Glitch eliminator circuit for TTL transparent latch

An improvement in output rise time and a reduction in the parasitic power supply strike current is achieved in bipolar transistor logic circuits using an AC coupled feedback circuit. During the low to high transition of the output, an internal voltage is AC coupled to an amplifier which in turn provides a low impedance path at the base of a lower output drive transistor which is coming out of conduction.

Circuit to improve rise time and/or reduce parasitic power supply spike

An improved fall time is achieved in bipolar transistor logic circuits which have three-state outputs. The circuits comprise a logic input terminal which is coupled to a push-pull output stage to drive a three-state output terminal. A three-state input receives three-state control signals for holding the output transistors in their non-conducting, high impedance state. Improved speed is achieved by adding a feedback circuit to remove stored base charge from the upper output driver transistor and to supply base current derived from the load to the lower output driver transistor during high to low transitions of the output voltage.

Growing community of inventors

Mesa, AZ, United States of America

Gordon H Allen