Rambus Inc.

Clearspeed Technology Limited

Maxim Integrated Products, Inc.

Acuid Corporation (guernsey) Limited

Gordon Faulds

Ray McConnell

Paul Winser

Ken Cameron

Eamon O'Dea

Dave Stuttard

Dave Williams

Phil Atkin

Tim Day

Trey Greer

John S Rhoades

Russell David

John Rhoades

Gajinder Singh Panesar

Jeff Bond

Anthony Spencer

Matthias Dejaegher

Danny Halamish

Simon McIntosh-Smith

Alexander Roger Deas

Igor Anatolievich Abrosimov

Allard Van Der Horst

Russel David

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.

Memory access consolidation for SIMD processing elements using transaction identifiers

An example method for generating bus addresses for slave devices on a two wire interface bus includes providing a base address to each of N slave devices connected to the two wire interface bus and providing a sequence of N&#x2212;1 clock pulses to each of the N slave devices to provide unique bus addresses. Circuitry within each of the example slave devices is operative to receive a base address followed by a plurality of clock pulses from the host device and to increment the base address by a digital integer. Circuitry within each of the example slave devices is further operative to terminate incrementing of the base address when an inhibit logic signal is detected at the slave program input and to save an address resulting from incrementing the base address as a bus address subsequent to terminating the incrementing of the base address.

System and method for automatically assigning bus addresses to slave devices

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Parallel date processing apparatus

A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.

Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions

A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Parallel data processing apparatus

A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream

A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements. The controller is operable to determine respective status information for a plurality of processing threads, and to control processing of the processing threads by the plurality of processors in dependence upon such status information.

A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.

A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to retrieve a plurality of incoming instruction streams in parallel with one another and operable to supply incoming instruction streams to one of a plurality of processing arrays.

Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution

An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

Data processing architectures for packet handling using a SIMD array

A data processing architecture comprising:

Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream

Data processing architectures

A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.

Growing community of inventors

Dursley, United Kingdom

Gordon Faulds