Micron Technology Incorporated

Gordon D Roberts

James E Miller, Jr

Jeffrey D Bruce

Manny K Ma

Eric T Stubbs

Daryl L Habersetzer

Kurt D Beigel

Douglas John Cutter

Brian M Shirley

Aaron M Schoenfeld

Lucien J Bissey

Bryan C Carson

Manny Kin F Ma

Darryl L Habersetzer

Kurt D Biegel

An integrated semiconductor memory chip includes hardwired presence detect data which can be accessed for transmission to a location external to the memory chip as well as logic allowing additional presence detect data to be programmed in the memory chip after fabrication of the memory chip. Storing the presence detect data on the memory chip rather than on a separate integrated circuit can help reduce the number of integrated chips required for a memory module, which may include multiple DRAM or other memory chips. Hardwiring at least some of the presence detect data during fabrication of the chip can reduce the number of programming errors as well as the number of mismatches that might otherwise occur if a separate presence detect data chip were used. On the other hand, the capability of programming presence detect data after fabrication of the memory chip provides additional flexibility, allowing the foregoing techniques to be used with a wide variety of memory chips and modules.

Integrated semiconductor memory chip with presence detect data capability

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Method of preparing to test a capacitor

Circuit and method for voltage regulation in a semiconductor device

Method of compensating for a defect within a semiconductor device

Driver circuit for a voltage-pulling device

Method of stressing a memory device

Method of testing a memory cell

Method of testing a memory array

Margin-range apparatus for a sense amp's voltage-pulling transistor

Methods of processing semiconductor circuits are disclosed. In one embodiment, a method of processing a semiconductor circuit includes isolating a conductive region of the semiconductor circuit from a substrate region of the semiconductor circuit while forming the semiconductor circuit, and connecting the conductive region to the substrate region after the forming of the semiconductor circuit is completed. In alternate embodiments, the isolating and connecting of the conductive and substrate regions may include de-activating and activating a transistor, respectively.

Method and apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connected to the substrate after manufacture

A device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the superimposed dice has at least one bond pad variably positioned on an active surface of the die. A plurality of lead fingers from a leadframe extend between the dice. The leadframe comprises at least one lead with leads of non-uniform length and configuration to attach to the differently positioned bond pads of the multiple dice. An advantage of the present invention is that it allows dice with differing bond pad arrangements to be used in a superimposed configuration to increase circuit density, while eliminating the use of bond wires in such a configuration.

Method and apparatus leads-between-chips

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a is plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Method of detecting a short from a digit line pair to ground

Growing community of inventors

Meridian, ID, United States of America

Gordon D Roberts