Analog Devices,inc.

Analog Devices Global Unlimited Company

Nanosemi, Inc.

Gordon Cheung

John A Hayden

Zohaib Mahmood

George Stone, Iv

Richard F Grafton

Dmitri Fomin

Hans Brueggemann

Bhupinder S Parhar

Ahmed Ali Mohamed

Matthew Puzey

James Frank Galeotos

Hans Brueggmann

Disclosed are methods, systems, devices, apparatus, media, design structures, and other implementations, including a method for crest factor reduction (CFR) processing that includes receiving a first complex-valued sample of a signal for radio transmission, determining a resultant clipped complex-valued sample for the first complex-valued sample, resulting from projection of a second complex-valued sample, associated with the first complex-valued sample, into a selected one of a plurality of different tangent lines that are tangential to a circle representation with a radius h in a complex-valued plane, and processing the signal using the determined clipped complex-valued sample to produce a resultant CFR signal.

Systems and methods for efficient clipping in crest factor reduction processes

Switching interference is a primary artifact which affects the accuracy of arc detectors. To address switching interference, conventional arc detectors employ computationally intensive techniques which are often designed specifically for a target application. Thus, conventional arc detectors require a significant amount of hardware to accurately detect arc faults, which can increase costs of the power systems and prohibit wide deployment of arc detectors. With improved signal processing, a unique method for arc detection can accurately detect arc faults efficiently while tolerate switching interference from an inverter of the power system. Specifically, the method provides accurate but efficient arc detection by using a small Fast Fourier Transform with coherent sampling that is accomplished with a common clock generator in combination with signal conditioning. The overall system implementing the method is also programmable to suit a variety of target applications.

Computationally efficient arc detector with coherent sampling

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Safety node in interconnect data buses

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Sudbury, MA, United States of America

Gordon Cheung