Motorola Corporation

Infineon Technologies Ag

Gordon C Ma

Gordon M Grivna

Christopher Paul Dragon

Hassan Pirastehfar

Steven J Adler

Richard A Keating

Nagaraj Vishwanath Dixit

A method of manufacturing a semiconductor component includes sequentially disposing a first electrically conductive layer (,), a dielectric layer (,), and a sacrificial layer (,) over a substrate (,). An etch mask is used to defined a gate stack (,) comprised of the sacrificial layer (,), the dielectric layer, and the first electrically conductive layer. Another dielectric layer (,) is deposited over the substrate (,) and the gate stack (,). This second dielectric layer (,) is planarized to expose the sacrificial layer (,). The sacrificial layer (,) of the gate stack (,) and the dielectric layer (,) of the gate stack (,) are sequentially removed, and another electrically conductive layer (,) is deposited over the first electrically conductive layer of the gate stack to form a gate electrode made of, among other features, two electrically conductive layers.

Method of manufacturing a semiconductor component

A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).

Semiconductor component and method of manufacture

An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.

Double implanted laterally diffused MOS device and method thereof

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Phoenix, AZ, United States of America

Gordon C Ma