Micron Technology Incorporated

Intel Corporation

Intel Corporatino

Gordon A Haller

Sanh D Tang

Hongbin Zhu

John David Hopkins

Luan C Tran

Jie Sun

Minsoo Lee

James Mathew

Charles H Dennison

Kirk D Prall

Ravi T Iyer

Thomas Arthur Figura

John Mark Meldrim

David A Daycock

Kunal Shrotri

Anish A Khandekar

Zhenyu Lu

Brett D Lowe

Tyler A Lowrey

Brian J Cleereman

Jun Zhao

Rita J Klein

Collin Howder

Yushi Hu

Merri Lyn Carlson

Darwin A Clampitt

Indra V Chary

Anilkumar Chandolu

Matthew J King

Kris K Brown

Hasan Nejad

Tuman Earl Allen, Iii

Randal W Chance

Randy J Koval

Jie Li

Yangda Zhang

Hongpeng Yu

Thomas George

Werner Juengling

Randhir P S Thakur

Roger W Lindsay

Andrew Bicksler

David J Keller

Prashant Raghu

Amitava Majumdar

Christopher J Larsen

Daniel Doyle

Matthew Park

Tom Jibu John

Ted Lyle Taylor

Prakash Rau Mokhna Rau

Shawn D Lyonsmith

Sri Sai Sivakumar Vegunta

Ahmed Nayaz Noemaun

Paul Grisham

Steve Cummings

John B Matovu

Qianlan Liu

Steve K McCandless

Lining He

Justin Harnish

Jia Hui Ng

H Jim Fulford

Fernando N Gonzalez

Jun Liu

Yongjun Jeff Hu

Pierre C Fazan

Fatma Arzum Simsek-Ege

Ronald Allen Weimer

D Mark Durcan

Philip J Ireland

Ceredig Roberts

David K Hwang

Paul D Shirley

Sanjeev Sapra

Vladimir Mikhalev

Lijing Gou

Purnima Narayanan

Damir Fazil

Vinayak Shamanna

Gowrisankar Damarla

Steven D Cummings

Lequn Jennifer Liu

William R Kueber

Taehyun Kim

Paul D Long

Jeremy F Adams

Trung Tri Doan

Mark E Tuttle

Randhir P Thakur

Kevin G Duesman

Michael P Violette

Shyam Surthi

Yauh-Ching Liu

Ruojia R Lee

Fei Wang

James E Davis

Darwin Franseda Fan

Wei Yeeng Ng

Wesley O McKinsey

A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.

System for predicting properties of structures, imager system, and related methods

Some embodiments include an integrated structure having a stack of memory cell levels. A pair of channel-material-pillars extend through the stack. A source structure is under the stack. The source structure includes a portion having an upper region, a lower region, and an intermediate region between the upper and lower regions. The upper and lower regions have a same composition and join to one another at edge locations. The intermediate region has a different composition than the upper and lower regions. The edge locations are directly against the channel material of the channel-material-pillars. Some embodiments include methods of forming an integrated assembly.

Integrated assemblies, and methods of forming integrated assemblies

A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Three dimensional memory

Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

A termination opening can be formed through the stack alternating dielectrics concurrently with forming contact openings through the stack. A termination structure can be formed in the termination opening. An additional opening can be formed through the termination structure and through the stack between groups of semiconductor structures that pass through the stack. In another example, an opening can be formed through the stack so that a first segment of the opening is between groups of semiconductor structures in a first region of the stack and a second segment of the opening is in a second region of the stack that does not include the groups of semiconductor structures. A material can be formed in the second segment so that the first segment terminates at the material. In some instances, the material can be implanted in the dielectrics in the second region through the second segment.

Forming terminations in stacked memory arrays

Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Semiconductor devices and methods of fabrication

A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells

Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

Integrated structures and methods of forming integrated structures

In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.

Formation of termination structures in stacked memory arrays

Growing community of inventors

Boise, ID, United States of America

Gordon A Haller