Qualcomm Incorporated

Goran Goran

Bohuslav Rychlik

Matthew Levi Severson

George Patsilaras

Andrew Edmund Turner

Jeffrey Gemar

Engin Ipek

Hamza Omar

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Providing content-aware cache replacement and insertion policies in processor-based devices

Growing community of inventors

Springfield, PA, United States of America

Goran Goran