Xilinx, Inc.

Goran Bilski

Ralph D Wittig

Satish R Ganesan

Usha Prabhu

Jennifer Wong

David B Squires

Paulo Luis Dutra

A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and put data between a general purpose register of a soft or hard core processor and a queue connected to a point-to-point communications channel. One implementation example is for a Fast Simplex Link multi-processor network.

Method and system for transferring data between a register in a processor and a point-to-point communication link

A fast linked multiprocessor network () including a plurality of processing modules (, and) implemented on a field programmable gate array () and a plurality of configurable uni-directional links () coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.

Method and system for fast linked processor in a system on a chip (SoC)

Various approaches for generating a clock accurate simulation model from a circuit design description are disclosed. In one approach, a graph representation of the circuit design description is created. The graph representation includes nodes and edges. From the nodes in the graph representation, a plurality of register nodes are generated to correspond to respective register functions. Logic optimization is performed on nodes that represent combinational logic functions. For each register node and each output node, an evaluation equation is generated after performing logic optimization. For each clock cycle of a logic simulation, each evaluation equation is evaluated and produces an output value for the next clock cycle.

Generating fast logic simulation models for a PLD design description

Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks

Efficient register circuits allow the loading of data values into a memory element using set and reset terminals in addition to loading via the data input terminal. A register circuit includes a memory element and a logical AND gate. A load command input terminal enables the load, and a load value input terminal provides the new value to be loaded. The memory element has set and reset terminals. In one embodiment, the reset function overrides the set function when both terminals provide active signals. The set terminal is coupled to the load command input terminal. The logical AND gate has input terminals coupled to the load command and load value input terminals, and an output terminal coupled to the reset terminal of the memory element. In another embodiment, the set function overrides the reset function, and the signals driving the set and reset terminals are reversed.

Efficient loadable registers in programmable logic devices

Structures and methods that reduce interconnect resource usage and routing delays in FPGAs by routing high fan-out signals on the CLB carry chains. In a first embodiment, a high fan-out signal distribution structure is implemented in a Field Programmable Gate Array (FPGA). The FPGA includes an array of logic cells, each including a carry multiplexer. The carry multiplexers can be configured to form a carry chain. The carry chain is used to distribute high fan-out signals by passing a high fan-out signal along the chain from carry-in terminal to carry-out terminal, and tapping the signal at the carry-out terminals for distribution to a large number of destinations.

Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers

Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or other logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.

ALU implementation in single PLD logic cell

Method for implementing electronic circuit designs that are adaptable to different binary data formats. Separate packages are provided for the different binary data formats. The names of the constants and subtypes are identical as between the packages, and the values associated with the constants and subtypes in each of the packages are particular to the associated data format. A selected one of the packages is imported into the. design, and selected references in the design to binary data are made using the names of the constants and subtypes set forth in the packages. The circuit design is then implemented by synthesizing and mapping the design to the selected device.

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San Jose, CA, United States of America

Goran Bilski