Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Gopu S

Binoy Jose Panakkal

Sainath Viswasarai

Bhavadip Bipinbhai Solanki

Subin Cp

Piyush Anil Dhotre

Ganapati Bhat

Lakshmi Sowjanya Sunkavelli

Pawan Negi

Aneesh Puthoor

Chittoor Devarajan Sunilkumar

Divya Prasad

Manoj M Shenoy

Swaroop Kaza

Narayan K

Salil Kale

Shreejith Kv

When an open block of NAND memory is read, this places the edge word lines under a set of bias conditions that can lead to disturbs. When time tag values are stored on predefined word lines, and the predefined word line is an edge word line, this can degrade not just the user data on the word line, but also the time tag values, leading to a failed bit count spike. To address this problem, a time tag word line shift approach is introduced where, if a predetermined time tag acquisition word line is an edge word line, another word line is instead used to acquire the time tag value.

Time tag word line shift to reduce failed bit count spikes for edge word lines

Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.

Sub-block mode (SBM) pre-charge operation sequences

A memory device includes a wordline zone table that stores information about how wordlines of one or more memory blocks are divided into wordline zones. The wordline zone table also stores a value associated with each wordline zone. When the memory device receives a command, a controller identifies a wordline associated with the command. The controller uses the wordline zone table to determine the wordline zone, and the value, associated with the wordline. The value is stored in a non-data wordline. When a find last good page (FLGP) process is initiated in response to an ungraceful device shutdown (UGDS) event, the controller determines the value stored in the non-data wordline. The controller compares the value in the non-data wordline to the values in the wordline zone table to determine which wordline zone matches the value. The FLPG process is applied to the wordline zone having the matching value.

Using a zone wordline table to initiate a find last good page process

A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB) through reverse order programming (ROP) so that the SBis pre-charged through the source side through the lower sub block (SB). Once the SBis written, data is then routed to the SBand then to the upper sub block (SB). When there is a garbage collection (GC) request, the FW will move the data from the SBand then erase the SB. Then the data moves from the SBand SBis erased. Finally, the data moves from the SBand then SBis erased.

Firmware scheme for 3 tier memories

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. Each non-volatile memory cell is configured to store a plurality of bits of a plurality of logical pages including at least a first bit of a first logical page, a second bit of a second logical page and a third bit of a third logical page. The control circuits are configured to select a subset of the plurality of logical pages for reading, perform pre-read steps, and read a first and at least a second selected logical page of the subset without performing pre-read steps between reading the first and second selected logical pages.

Nonvolatile memory with combined reads

Apparatuses, systems, methods, and computer program products for enhanced erase retry of a non-volatile storage device are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a verification component configured to detect that an erase operation performed on an erase block of a non-volatile storage device is unsuccessful. A controller includes a parameter component configured to adjust one or more erase parameters for an erase operation. One or more erase parameters may be associated with one or more select gate drain storage cells of an erase block. A controller includes an erase component configured to retry an erase operation on an erase block with one or more adjusted erase parameters.

Enhanced erase retry of non-volatile storage device

Apparatuses, systems, and methods are disclosed for read threshold adjustment using reference data for non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to write a predetermined reference data pattern to a region of an array. A controller may be configured to read reference data from a region. A controller may be configured to set one or more read thresholds based on identifying differences between reference data and a predetermined reference data pattern.

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Trivandrum, India

Gopu S