Sandisk Technologies Inc.

Sandisk 3d LLC

Kabushiki Kaisha Toshiba

Gopinath Balakrishnan

Tz-Yi Liu

Luca Giovanni Fasoli

Yuheng Zhang

Chang Hua Siau

Tianhong Yan

Yan Li

Jeffrey Koon Yee Lee

Grishma Shah

Yingchang Chen

Anurag Nigam

Kapil Verma

Yibo Yin

Eran Sharon

Idan Alrod

Ariel Navon

Robert W Ellis

Aaron Keith Olbrich

Jack Frayer

Takahiko Sasaki

Ishai Ilani

Vidyabhushan Mohan

Kenneth Louie

Ashish Ghai

Wanfang Tsai

Lakshmi Kalpana Vakati

Yosuke Kato

Ekamdeep Singh

Henry Zhang

Shingo Zaitsu

Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.

Multi-die rolling status mode for non-volatile storage

Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.

Leakage current detection in 3D memory

Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

Independent sense amplifier addressing and quota sharing in non-volatile memory

A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles.

Regrouping and skipping cycles in non-volatile memory

Sensing techniques and associated circuitry are provided for use with a memory device. The techniques are suited for sensing operations involving even-numbered or odd-numbered bit lines. In one approach, the sensing circuitry includes left and right hand portions which have separate cache access lines, but are connected to a common output bus. A full data word can be output at a time by using a half word from the left hand portion and a half word from the right hand portion. Or, the sensing circuitry can be configured so that a full data word is output at a time from the left or right hand portion. One implementation provides an N-bit bus and N input paths for each of the left and right hand portions. Another implementation provides an N-bit bus and N/2 input paths for each of the left and right hand portions.

Fast read for non-volatile storage

According to one embodiment, a temperature sensor includes: a voltage generating part generating (2&#x2212;1)-midpoint voltages (N is a natural number equal to or larger than 2) based on a reference voltage which does not depend on a temperature; a sense part generating a temperature sensing voltage which depends on the temperature; and an arithmetic part is configured to generate N-bit temperature data by executing first to N-th operations each comparing the temperature sensing voltage with one of the (2&#x2212;1)-midpoint voltages.

Temperature sensor with successive AD conversion with selective comparisons

A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Program cycle skip

A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Apparatus and methods for sensing hard bit and soft bits

Determining dynamic read levels for memory cells is disclosed. A group of memory cells may be read at a pair of reference levels. Results of reading the group at the pair of reference levels are compared while the group is read at a different reference level. By comparing the results of reading the group at the pair of reference levels while reading the group at a different reference level, time is saved. Note that the reading and comparing can be repeated for other pairs of reference levels. The storage device may determine an adjusted read level based on the comparisons of the results for the different pairs of reference levels. The memory cells may be read at a set of reference levels. A voltage on a word line is not back down to ground between the reads in one aspect, which saves considerable time.

Dynamic read valley search in non-volatile memory

A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.

Page buffer program command and methods to reprogram pages without re-inputting data to a memory device

A programming technique for a set of resistance-switching memory cells such as ReRAM cell involves programming the low resistance cells to the high resistance state (in a reset process) early in a programming operation, before programming the high resistance cells to the low resistance state (in a set process), to minimize losses due to leakage currents. The reset process can be performed in one or more phases. In some cases, a current limit is imposed which limits the number of cells which can be reset at the same time. Initially, the cells which are to be reset and set are identified by comparing a logical value of their current resistance state to a logical value of write data. If there is a match, the cell is not programmed. If there is not a match, the cell is programmed.

Methods for programming ReRAM devices

Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

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Santa Clara, CA, United States of America

Gopinath Balakrishnan