International Business Machines Corporation

Gopikrishnan Viswanadhan

Dharmesh Parikh

Anil Pothireddy

Jayashri Arsikere Basappa

Neranjen Ramalingam

A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.

Managing cache coherence for memory caches

A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a 'load intensive' device or as a 'store intensive' device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the &#x201c;outbound&#x201d; and &#x201c;inbound&#x201d; buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either &#x201c;load intensive&#x201d; or &#x201c;store intensive&#x201d; mode. The invention is applicable for use with all types of communications network switches (i.e. &#x201c;Bridges&#x201d;, &#x201c;Hubs&#x201d;, &#x201c;Routers&#x201d; etc.).

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Bengaluru, India

Gopikrishnan Viswanadhan