Texas Instruments Corporation

Silab Tech Pvt. Ltd.

Gopalkrishna Nayak

Sujoy Chakravarty

Jayawardan Janardhanan

Biman Chattopadhyay

Ravi Mehta

Somasunder Kattepura Sreenath

Vikas Kumar Sinha

Matthew Craig Bullock

Shivaprakash Halagur

A system and method for managing estimation and calibration of non-ideality of a Clock and Data Recovery circuit includes phase interpolators (PIs), first and second sets of delay elements, and a clock delay element. A first delay element of the first set of delay elements is programmed using a first digital delay control code (DDCC). The clock delay element is calibrated using a digital external delay control code (DEDCC) till a predetermined criterion is met, and is retained for subsequent use. The remaining delay elements of the first set of delay elements are separately calibrated based on the DEDCC. A first delay element of the second set of delay elements is programmed using a second DDCC. The DEDCC is readjusted for the second set of delay elements. The remaining delay elements of the second set of delay elements are separately calibrated based on the readjusted DEDCC.

Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (PI)-based clock and data recovery (CDR) circuit

A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal. The data bus synchronizer further includes a logic block configured to generate the load enable signal on satisfaction of a logic condition.

Data bus synchronizer without an enable signal input

In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.

Determining optimum code from default, programmable, and test trim codes

A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

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Gopalkrishna Nayak