Texas Instruments Corporation

Gopalaro Kadamati

Charvaka Duvvury

Sridhar Ramaswamy

Snehamay Sinha

Guru Chakrapani Prasad

Puvvada Venugopal

C S Raghu

For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.

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Plano, TX, United States of America

Gopalaro Kadamati