Texas Instruments Corporation

Gopalarao Kadamati

Ranjit Gharpurey

Sridhar Ramaswamy

Snehamay Sinha

For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.

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Plano, TX, United States of America

Gopalarao Kadamati