Edgeq, Inc.

Cypress Semiconductor Corporation

Netlogic Microsystems, Inc

Gopalakrishnan Perur Krishnan

Hariprasad Gangadharan

Vishwanatha Tarikere Basavaraja

Eswar Vadlamani

Sriram K Rajagopal

Yansun Xu

Vinay Ravuri

Umesh Dattatraya Nimbhorkar

Chaekwan Lee

Tarjinder Singh

Tarjinder Singh Munday

Vivek Goyal

Ramesha Doddamane

Tae Ryun Chang

Advances in wireless technologies have resulted in the ability of a wireless communication system to support wireless communications of different standards, e.g., 5G, LTE, and Wi-Fi. Different Wireless standards have aspects which are very different from each other. Described in the present disclosure are embodiments of architecture with hardware and software split to allow implementation of different wireless standards along a configurable signal process path. The configurable signal process path comprises software configurable operators that may be configured in a desired level of granularity to load desirable software to process signals of various standards on the same hardware. Embodiments of the disclosed architecture with hybrid hardware and software implementation may improve system operation efficiency and lower system complexity to serve communications across multiple wireless standards.

Systems and methods for hybrid hardware and software implementation of multiple wireless standards

With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. In the present disclosure, two baseband processors are used with each processor dedicated for one type of signal processing, such as 5G or Wi-Fi. The two baseband processors are interlinked via a chip-to-chip interconnect link for ingress and egress data transfer between the two processors. These two processors share an Ethernet link for benefits including cost saving, reduction in overall chipset power, and reduced form factor of the enclosure. Application of the disclosed embodiments may realize concurrent 5G Fronthaul and Wi-Fi traffic processing on the same Ethernet link. Such an application may be applied to other related scenarios, including Ethernet link sharing for dual Wi-Fi baseband processors, and Ethernet link sharing for Wi-Fi and gNodeB deployments, etc.

Systems and methods for ethernet link sharing to concurrently support multiple radios

Enhanced Common Packet Radio Interface (eCPRI) based Fronthaul forms the foundation for open radio access network (O-RAN). O-RAN envisages splitting the radio into two parts, a Distributed Unit (DU) and Radio Units (RU), interconnected using high speed Fronthaul links. O-RAN and eCPRI for 5G/NR place demands for high speed Fronthaul with low latency, and high network bandwidth requirements. In the present disclosure, embodiments for configurable eCPRI Fronthaul solutions are disclosed. Various hardware accelerator implementations are presented for control plane and user plane traffic. The hardware accelerator implementation may support DU and RRU functionality required by eCPRI with minimal software intervention. The configurable eCPRI Fronthaul may support different data flows and meet different performance demands of DU and RRU. Scalable architecture may be applied for the configurable eCPRI Fronthaul to allow stacking of multiple hardware accelerators via a high-speed network interconnect, and overall performance and throughput may be improved.

Systems and methods for front haul traffic processing on radio units and distributed baseband units

A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator () that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (). An address range selector circuit () can limit the range of addresses generated by an address generator (). Once defective addresses for a first range have been detected, an address range selector circuit () can test another range. An entire address range can thus be tested regardless of the depth of a fault address store ().

Programmable address space built-in self test (BIST) device and method for fault detection

An averaging circuit and method are provided to compute a running average over a number of samples without the need for maintaining a large sample queue or register. Generally, the method includes the steps of (i) receiving and accumulating data samples in a plurality of sample-accumulators while counting the number of samples received in a sample-counter; (ii) alternately selecting the sum of the samples accumulated in each of the sample-accumulators; (iii) dividing the sum of the samples accumulated in a selected sample-accumulator by the number of samples received to provide an average of the samples accumulated therein; and (iv) interleaving selection of the plurality of sample-accumulators and alternating reset of each to provide a running average over a number of samples.

Signal averaging circuit and method for sample averaging

A parallel data transmission test system can include a receiver section () having input selector circuits (-O to-N) that provide a received test data to logic adjust circuits (-O to-N) that 'logically align' multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit () can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit ().

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Bengaluru, India

Gopalakrishnan Perur Krishnan