Intrinsity, Inc.

Motorola Corporation

Gopal Vijayan

Stephen C Horne

Donald W Glowka

James S Blomgren

Alexander Mikhailovich Marchenko

Andrey P Plis

This invention discloses a software tool that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool includes a routing rule generation tool that creates a route rule database for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool . The routing rule generation tool further includes a noise sensitivity/gate characterization tool and a rule generator tool . The block build tool further includes a gate sizing tool , a gate analysis tool , a route rule selecting tool , a route assigning tool

Generation of route rules

The invention relates to a method for manufacturing of electronic devices, such as very large scale integrated devices, having a channel. The channel routing is done based on a compositional approach in which initially all individual terminals are represented by individual nodes in a terminal vertical constraint graph. Individual constraints between individual terminals are represented by separate edges. This approach allows the resolution of difficult classes of routing problems in an efficient way.

Method for manufacturing and designing a wiring of a channel of an electronic device and electronic apparatus

The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer , a levelizer , a backward logic scanner , a forward logic scanner , a gate target delay incrementor , and a gate target delay comparator that together calculates the propagation delay of a signal in a specified block of dynamic logic.

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Austin, TX, United States of America

Gopal Vijayan