Inphi Corporation

Eta Compute, Inc.

Hrl Laboratories, LLC

Hughes Electronics Corporation

Hughes Aircraft Company

The Boeing Company

Raytheon Company

Gopal Raghavan

Carl W Pobanz

Joseph F Jensen

Albert E Cosand

Chao Xu

Michael G Case

Christopher Haywood

David Cureton Baker

Bryan Garnett Cope

Henrik T Jensen

Jeffrey C Yen

Ben Wiley Melton

Vidura Manu Wijayasekara

Dhruv Jain

John Whitaker Havlicek

Nikhil K Srivastava

Howard S Nussbaum

William P Posey

Paul Murtagh

Joseph J Jensen

There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

Self-timed processors implemented with multi-rail null convention logic and unate gates

There is disclosed a self-timed clocked synchronous processor having at least one combinatorial logic (CL) block for processing data. The CL block has a critical path with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block at an operating voltage of the processor without a timing error due to a register of the processor receiving the critical path output before it is completed. The processor has a critical path oscillator to simulate the critical path propagation delay and create an oscillator clock signal with a period greater than the minimum allowable clock period. The oscillator clock signal is used to clock the register, avoiding the timing error. A power manager outputs an operating voltage to the processor that causes the oscillator clock to be faster than an external time reference period for completing the current task of the processor.

Self-timed clocked processor architecture

Temperature-independent clock generation systems and methods are described that include a trained neural network coupled to a frequency correction circuit that corrects a crystal resonator output of a clock signal having a frequency that changes with changes in temperature. The neural network is trained with test temperatures and corresponding temperature based changes in frequency for test resonators of the same type as the resonator of the real time clock. The neutral network is trained to output frequency corrections based on a set of measured reference temperature-based changes in frequency for the crystal resonator and a current temperature of the resonator. The frequency correction circuit receives the frequency corrections from the neural network and corrects changes in the frequency caused by the changes in temperature of the resonator to provide a clock signal having an output frequency that is independent of the current temperature of the resonator.

Real time clock with neural network correction of temperature-based changes in frequency

There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device includes an asynchronous processor operative from an operating voltage and a voltage regulator circuit. The asynchronous processor includes a collection of asynchronous logic circuits that are collectively capable of executing stored instructions. The voltage regulator circuit receives a voltage request from the asynchronous processor and outputs the operating voltage to the asynchronous processor as defined by the voltage request.

Asynchronous processor

There are disclosed asynchronous computing devices and methods of operating asynchronous computing devices. An asynchronous computing device may include an asynchronous processor and a voltage regulator circuit that outputs an operating voltage to the asynchronous processor in response to a voltage request received from the asynchronous processor.

Asynchronous processor that adjusts a respective operating voltage for causing a task to consume substantially all of a respective allocated time interval for the task

A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.

Redriven/retimed registered dual inline memory module

A load reduction system and method for use with memory systems which include one or more DIMMs, each of which includes a circuit arranged to buffer data bytes being written to or read from the DIMM, with the system nominally organized such that the bytes of a given data word are conveyed to the DIMMs via respective byte lanes and stored in a given rank on a given DIMM. The system is arranged such that the DRAMs that constitute a given rank are re-mapped across the available DIMMs plugged into the slots, such that a data word to be stored in a given rank is striped across the available DIMMs, thereby reducing the loading on a given byte lane that might otherwise be present. The system is preferably arranged such that any given byte lane is wired to no more than two of the DIMM slots.

Load reduction system and method for DIMM-based memory systems

An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a 'normal' mode, and a second output impedance which is greater than the first output impedance when operated in a 'standby' mode. By increasing the drive circuit's output impedance while in &#x2018;standby&#x2019; mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in &#x2018;standby&#x2019; mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.

Output buffer with switchable output impedance

A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKand generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (t) between the toggling of CKand a resulting change at the slave latch's output less than it would otherwise be.

Master-slave flip-flop and clocking scheme

A programmable strength output buffer intended for use within the address register of a memory module such as a registered DIMM (RDIMM). The output signals of an array of such buffers drive respective output lines that are connected to the address or control pins of several RAM chips. The programmable buffers vary the strength of at least some of the output signals in response to a configuration control signal, such that the output signals can be optimized for the loads to which they will be connected.

Programmable strength output buffer for RDIMM address register

An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage Vto a voltage V; a second portion during which it remains fixed at V; a third portion during which it transitions to a voltage V; and a fourth portion during which it remains fixed at V. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that Vis maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

Output buffer with time varying source impedance for driving capacitively-terminated transmission lines

A bipolar transistor-based linearizer with programmable gain and phase response apparatus uses a splitter to separate an incoming RF signal into two equal components: in-phase (I) and quadrature (Q, ninety degrees delayed). The I signal then passes through a first bipolar variable gain amplifier (VGA) while the Q signal passes through a second bipolar VGA. After passing through the first and second VGAs, the amplified signals are combined at the output using a summer to produce a predistorted signal that drives a TWTA. The gains of each VGA are controlled using an RF power detector in conjunction with a bipolar gain/phase slope controller. Each gain can be adjusted separately to product a large range of linearization characteristics.

Bipolar transistor-based linearizer with programmable gain and phase response system

An effective means and apparatus for generating a negative resistance including a circuit element that exhibits an increase in current as the applied voltage is decreased. Other embodiments of the present invention provide electronic means for improving the quality Q factor of on-chip resonators, which enables the creation of high-performance bipolar RF circuits with a minimum of external components.

Variable negative resistance cell for bipolar integrated circuits

An apparatus and method of improving linearity of a multi bit &Dgr;&Sgr; modulator in which the output of a multi-bit quantizer of a &Dgr;&Sgr; modulator is connected in a feedback loop to a converter where output is a higher frequency single bit data stream which is supplied to a 1-bit digital to analog converter whose output is fed back to the quantizer to provide linearity of the output of the &Dgr;&Sgr; modulator.

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Thousand Oaks, CA, United States of America

Gopal Raghavan