Huawei Technologies Co., Limited

Other

Gongyi Wang

Jianqiang Shen

Yanxing Zeng

Shaohui Quan

Jinyi Zhang

Kun Guan

Tao Li

Sheng Chang

Ruliang Dong

Qiang Xue

Yafei Zhao

Ben Chen

Aleksei Valentinovich Romanovskii

Wen Lv

Haixiao Jiang

Jinan Leng

Aleksei Romanovskii

A data compression method includes obtaining N to-be-compressed data blocks and N pieces of protection information (PI), where the N to-be-compressed data blocks are in a one-to-one correspondence with the N pieces of PI, and N is a positive integer greater than or equal to 2, compressing the N to-be-compressed data blocks to obtain a compressed data block, and compressing the N pieces of PI to obtain compressed PI.

Data compression method, data decompression method, and related apparatus

A method for obtaining a storage system capacity is provided. An available capacity that is of a storage system and that is associated with each stripe length is obtained based on an obtained stripe length that can be effectively configured. Therefore, an available capacity of a system is optimally selected.

Method and apparatus for calculating storage system available capacity

A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)read voltage threshold and the data obtained by reading the flash memory page using the mread voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.

Flash memory error correction method and apparatus

A node controller-based request responding method and node controller, where the method includes receiving, by a first node controller, a first packet, acquiring an information directory, and querying, in the information directory, whether a memory address requested by the first packet is occupied by a second node controller, and when the memory address requested by the first packet is occupied by the second node controller, querying node presence information to determine whether the second node controller exists, and when it is determined that the second node controller does not exist, generating and sending an invalid response packet.

Node controller and method for responding to request based on node controller

An encoding method and apparatus is described. In an encoding method, when a first target sub-block in a target block is obtained, a hash operation is first performed on the first target sub-block. Then, a first hash table is queried for a corresponding hash value according to an operation result, and a corresponding location in a reference block is found according to the hash value obtained by means of query, that is, first reference data is found. The first piece of target data in the first target sub-block is matched with the first reference data, and second target data in the target block is matched with second reference data in the reference block. In this way, an approximate location is predetermined, so that a range in which matching needs to be performed is narrowed, a data compression time is reduced, and data compression efficiency is improved.

Encoding method and apparatus

This application discloses a storage controller. When running, the storage controller encodes, according to a check matrix, K to-be-coded data chunks obtained from a client, to generate two check chunks. In this way, if any chunk is damaged subsequently, the damaged chunk may be recovered by using the check matrix and an undamaged chunk.

Storage controller, data processing chip, and data processing method

A storage expansion apparatus and a server, where the storage expansion apparatus includes a quick path interconnect (QPI) interface module, which communicates with a central processing unit (CPU) through a QPI bus; a peripheral component interconnect express (PCIe) interface module, which communicates with the CPU through a PCIe bus; an interface selecting module, connected to the QPI interface module and the PCIe interface module separately; a home agent (HA) module, connected to the interface selecting module; and a memory controller engine (MCEng) module, connected to the HA module and the interface selecting module separately. The storage expansion apparatus may serve as a CPU memory capacity expansion device, and may also serve as storage expansion hardware of storage input and output (TO).

Growing community of inventors

Hangzhou, China

Gongyi Wang