Samsung Electronics Co., Ltd.

Gong-Heum Han

Bo-Tak Lim

Hyou-Youn Nam

Soon-Moon Jung

Choong-Keun Kwak

Chul-Sung Park

Hoon Lim

Jang-Woo Ryu

Han-Byung Park

Tae-Seong Jang

Hoi-ju Chung

Chang-Yong Lee

Tae-Young Oh

Jong-Pil Son

Jae-Wook Lee

Joon-Min Park

Su-Yeon Kim

Chan-yong Lee

Min-soo Jang

In-Cheol Shin

Kyeong-Yoon Bae

Cheol-Sung Park

A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.

Semiconductor memory device, memory system, and method using bus-invert encoding

An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.

Address aligner and memory device including the same

A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.

Memory devices that perform masked write operations and methods of operating the same

In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

Semiconductor memory devices, memory systems including the same and method of writing data in the same

A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

Semiconductor memory device having three dimensional structure

A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

Semiconductor memory device having a peripheral region including operating capacitors

A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.

Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof

Semiconductor device having three dimensional structure

Semiconductor memory device and method for arranging and manufacturing the same

A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

Semiconductor memory device for low power consumption

A semiconductor memory device employs a power supply system in which a first power supply voltage supplied to a cell area is separated from a second power supply voltage supplied to a peripheral circuit area. Particularly, during a wafer burn-in test operation mode, the first power supply voltage supplied to the cell area is higher than the second power supply voltage supplied to the peripheral circuit area. If a wafer burn-in test operation is performed under the second power supply system, a DC current path formed by a latch-up phenomenon of a memory cell can be shut off.

Semiconductor memory device and test method therof

A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (t ) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.

Semiconductor memory device having reduced chip select output time

A semiconductor memory device is provided which uses an externally applied power supply voltage as its operating voltage. The device comprises plural memory cells each arranged in intersections of word lines and bit lines. The device further comprises an internal power supply voltage generating circuit for receiving the externally applied power supply voltage to generate an internal power supply voltage of a first level. Furthermore, the device has a plurality of word line drivers each connected to the word lines and to a power node for receiving the internal power supply voltage. The each of the word line drivers drives a corresponding word line with the internal power supply voltage in response to a word line selection signal. According to the semiconductor memory device of the present invention, a potential on the word line becomes maintained constantly at the operating voltage even though the external power supply voltage is increased. This prevents bit lines from becoming charged more than a required level owing to an external power supply voltage variation, so that signal swing width on each bit line and a write recovery time becomes maintained constantly. As a result, there is few or no power consumption in association with an external power supply voltage variation.

Growing community of inventors

Gyeonggi-do, South Korea

Gong-Heum Han