Industry-university Cooperation Foundation Hanyang University

Siltron, Inc.

Other

Jea Gun Park

Gon-Sub Lee

Jea-Gun Park

Sang-Hee Lee

Tae-Hyun Kim

Dong-Won Shin

Sung-Ho Seo

Tae-Hun Shim

Seong-Je Kim

Jae-Gun Park

Su-Hwan Lee

Woo-Sik Nam

Dal-Ho Kim

Hyun-Min Seung

Jong-Dae Lee

Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

Capacitor-less memory device

Provided is a method of driving a display panel having a charge trap device and an organic light emitting diode (OLED). The charge trap device includes a nanocrystal layer. The nanocrystal layer includes nanocrystals, which are crystallized and dispersed, and a barrier layer, which buries the nanocrystals. When a program voltage is applied, charges are trapped in the nanocrystals, and the OLED emits light at a predetermined luminance with the application of a read voltage. Data signals are sequentially applied to all pixels of the display panel to express desired grayscales. The pixels of the display panel receive the read voltage and emit light at the same time.

Method of driving display panel

A method of fabricating a nano silicon on insulator (SOI) wafer having an excellent thickness evenness without performing a chemical mechanical polishing (CMP) and a wafer fabricated by the same are provided. The provided method includes preparing a bond wafer and a base wafer, and forming a dielectric on at least on surface of the bond wafer. Thereafter, an impurity ion implantation unit is formed by implanting impurity ions into the bond wafer to a predetermined depth from the surface of the bond wafer at a low voltage. The dielectric of the bond wafer and the base wafer contact each other in order to be bonded. Next, a thermal process of low temperature is performed to cleave the impurity ion implantation unit of the bond wafer. In addition, the cleaved surface of the bond wafer bonded to the base wafer is etched to form a nano scale device region. Here, the cleaved surface may be etched by performing a hydrogen surface process and a wet etching.

Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same

Growing community of inventors

Seoul, South Korea

Gon-Sub Lee