Hyundai Electronics Industries Co. Ltd.

Boe Hydis Technology Co., Ltd.

Gon Son

Jae Kap Kim

Hae Sung Park

Young Il Park

Dong Hae Suh

Soo Young Choi

Mi Young Kang

Sea C Kim

Jin Ki Jung

Dong Duk Lee

Heon C Lee

Soo S Yoon

Disclosed is a method for forming an alignment layer of an LCD capable of preventing Mura defects when the alignment layer is formed through an LC one drop fill process. The method includes the steps of coating a mixing solution including a solvent and organic polymer materials consisting of polyimide and polyamic acid on the substrates, pre-curing the mixing solution twice with mutually different temperatures, thereby volatizing the solvent and obtaining stable phase-separation between the organic polymer materials and the solvent, and completely curing the pre-cured mixing solution at a temperature of about 180 to 240&#xb0; C. A primary pre-curing process is performed at a temperature less than 50&#xb0; C. under vacuum pressure of about &#x2212;35 to &#x2212;50 psi, and a secondary pre-curing process is performed at a temperature within a range of about 50 to 75&#xb0; C. under the same vacuum pressure.

Method for forming alignment layer of LCD

A method for forming a via hole in multiple metal layers of the semiconductor device is disclosed. In a via hole forming process of the semiconductor device, a barrier layer is formed beneath the photoresistive layer. Accordingly, the polymer residue formed on the metal-layer pattern and side wall of the via hole is prevented during the plasma etching process.

Method for forming via hole in multiple metal layers of semiconductor

The present invention relates to a manufacturing method of a contact of a multi-layered metal line of a highly integrated semiconductor device. The insulating layer between the metal lines is flattened and step coverage is improved by using a SOG layer or polyimide.

Contact manufacturing method of a multi-layered metal line structure

A method of forming a contact region having an insulating layer which is etch protected, which includes sequentially depositing a gate oxide layer 2, a first conducting layer 3 for gate electrode, a first insulating layer 4 and a second conducting layer 5 on a silicon substrate 1. A portion of the second conducting layer 5 is etched to form an etch protective layer 5A. Portions of the etch protective layer 5A, the first insulating layer 4 and the first conducting layer 3 are sequentially etched to form separated gate electrodes 3a and 3b and separated etch protective layers 5a and 5b on the gate electrodes 3a and 3b, respectively and to expose a portion of the gate oxide layer 2 to define a source region 1A. A second insulating layer 6 is deposited on the entire surface of the resulting structure. The second insulating layer 6 is etched to form a spacer 6a on each of the side walls of the gate electrodes 3a and 3b and on the first insulating layer 4 and to expose the source region 1A. A third insulating layer 7 is deposited on the entire surface of the resulting structure. A contact region 10 is formed by selectively removing the third insulating layer 7 and the gate oxide layer 2 on the source region 1A and portions of the third insulating layer 7 on the etch protective layers 5a and 5b to form a contact region having an etch protected insulating layer.

Method of forming a self-aligned contact utilizing a polysilicon layer

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Kyoungki-do, South Korea

Gon Son