Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Golan Schzukin

Aviran Kadosh

Ofer Iny

Eyal Dagan

Itay Admon

Gabriel Bracha

Dikla Tzafrir

Ariel Shchigelski

Gil Greenstein

Yahav Yechiel Shifman

Amir Levy

Alex Kertsman

A switching device includes a primary memory and an traffic manager. The primary memory buffers packets for temporary storage. The traffic manager monitors consumed resources in the device related to the buffering of packets in the primary memory. The traffic manager migrates packets buffered in the primary memory to a secondary memory when the consumed resources exceed a certain threshold. The traffic manager also controls dequeuing of the packets from the primary memory and the secondary memory.

Hierarchical packet buffer system

The present disclosure is directed to a system and method for performing out-of-order message filtering with aging. The system and method can be used in a destination device that can receive messages out-of-order (i.e., in a different order than they were transmitted) from a source device. The system and method can filter-out or flag for appropriate handling these messages received out-of-order. To perform the above noted message filtering functionality, the system and method uses a database constructed from a content-addressable memory (CAM) and a random-access memory (RAM) to respectively remember source identifiers and sequence identifiers associated with previously received messages. A source identifier identifies the source of a message, and a sequence identifier identifies the transmission order of the message among the messages transmitted from the particular source. Each message can include a source identifier and a corresponding sequence identifier.

Out-of-order message filtering with aging

A method and apparatus for more efficient routing of packets in a network is provided. The apparatus may include dynamic routing of packets or portions of packets which avoids congestion and blocking by making local decisions within the network. The apparatus may further include creating and updating routing tables which map switch outputs to available network output ports. Additionally the header of packets entering the network are processed prior to entry or as part of the entry to the network to produce a processed packet. The processed packets or portions of packets preferably include complete route information or a final destination address that enables rapid routing through the network without further processing of the packet header. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further improve network efficiency.

Method and apparatus for routing in a single tier switched network

A method and apparatus that controls the clock of a digital circuit, and therefore power consumption, without substantially comprising performance is provided. The apparatus may include monitoring the utilization of a First in First Out (FIFO) buffer. For example in a systems and methods according to the invention, clock speed may be reduced when the FIFO is relatively empty and increased when the FIFO is relatively full. The clock speed may be controlled by a phase locked loop, a clock divider, a clock masking device or a combination of more than one of these methods. Power reduction may also be obtained by controlling the clocking of different stages of a pipelined device. One or more aspects of the inventions may be implemented in combination with other aspects of the invention to further reduce power use.

Method and apparatus for reducing power consumption in a digital circuit by controlling the clock

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Herzliya, Israel

Golan Schzukin