Silicon Laboratories Inc.

Advanced Micro Devices Corporation

Cirrus Logic Inc.

Synaptics Corporation

Golam Rasul Chowdhury

Douglas R Holberg

Douglas F Pastorello

Biranchinath Sahu

Douglas S Piasecki

Arjang Hassibi

Bryan Garnett Cope

Kartika Prihadi

Mark Alexander

William Durbin

Krishnan Subramonium

Michael A Nix

Steve Chikin Lo

Faisal A Syed

Curtis M Brody

Mucahit Kozak

Bruce Del Signore

Kevin Kwak

A digital to analog convertor comprises an output line; first, second and third pluralities of capacitors; and first and second bridge capacitors. The first plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a first least significant bit capacitor of a first capacitance value. The second plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a second capacitor of the first capacitance value. The third plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a third capacitor of the first capacitance value. The first bridge capacitor bridges the output line between the first plurality of capacitors and the second plurality of capacitors. The second bridge capacitor bridges the output line between the second plurality of capacitors and the third plurality of capacitors.

Successive approximation register analog to digital converter with multiple split digital to analog convertors

A method and apparatus for determining a temperature of a semiconductor device is provided herein. One aspect of the disclosed subject matter is seen in a temperature sensing device. The temperature sensing device comprises a diode and a circuit. The diode is adapted to be reverse biased by a charging voltage applied thereto. The circuit determines a temperature of the diode based on a rate that the voltage on the diode discharges in response to the charging voltage being uncoupled from the diode.

On-chip temperature sensor

A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.

On-chip power-up control circuit

The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.

Programmable I/O cell capable of holding its state in power-down mode

A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.

Microcontroller unit (MCU) with power saving mode

A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.

Coding method for digital to analog converter of a SAR analog to digital converter

MCU with power saving mode

A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.

Method and apparatus for tuning GMC filter

The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.

Method for search and matching of capacitors for a digital to analog converter of an SAR analog to digital converter

A sampling network comprises analog comparator for comparing an analog voltage to a plurality of successive voltage inputs. A plurality of capacitors are connected in parallel with a first end of each of the capacitors coupled to the first input of the analog comparator to provide one of the successive voltage inputs. A first plurality of switches includes one switch associated with each of the plurality of capacitors to connect an input voltage to the second end of the capacitor. A bulk of a switch of the first plurality of switches is connected to the input voltage while the input voltage is being sampled and to a power supply voltage while the reference voltage is being sampled. A second plurality of switches is in parallel with the first plurality of switches and further includes one switch connected to each of the plurality of capacitors. The second plurality of switches connect a reference voltage to a second end of the capacitor. A bulk of a switch of the second plurality of switches is connected to the reference voltage while the reference voltage is being sampled and to the power supply voltage while the input voltage is being sampled.

Bulk-compensated sampling network for wide range of signals

An attenuator includes a first stagehaving a first operational amplifierand a tapped resistor. Tapped resistorhas an input for receiving input data, an output coupled to an output of first operational amplifier, and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of first operational amplifier. Each of these sequences of voltages corresponds to an attenuation step such that first stagesteps the attenuation produced by the attenuator from an intermediate value to a predetermined ending value. A second stageincludes a second operational amplifierand a tapped resistor. Tapped resistorincludes an input for receiving analog data from first stage, an output coupled to an output of second operational amplifier, and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of operational amplifier. Each of the sequence of voltages corresponds to an attenuation step, a second stagestepping the attenuation from a predetermined starting value to the intermediate value.

Multiple stage attenuator

Audio data processing circuitry,includes a plurality of analog inputs,for receiving analog audio data and a digital input,for receiving digital audio data. A analog mixer,mixes analog data received at said plurality of analog inputs,to generate a mixed analog audio stream. An analog-to-digital converter,converts the mixed analog audio stream to a digital audio stream and a digital mixer,mixes digital data received at the digital input,with the digital audio stream from the analog mixer,to generate a mixed digital audio stream.

Growing community of inventors

Austin, TX, United States of America

Golam Rasul Chowdhury