Apple Inc.

Gokul V Ganesan

Sean M Reynolds

A method and apparatus for performing an indexed data dependency instruction wakeup is disclosed. A scheduler may issue one or more instruction operations from a number of entries therein, including a first instruction operation. In a second entry, a comparison operation may be performed between a dependency index and an index of the first instruction operation. A match between the index of the first instruction and the dependency index in the second entry indicates a dependency of the corresponding instruction on the first instruction, and further indicates that the first instruction operation has issued. The dependency may be determined based solely on the match between the dependency index and the index of the first instruction. Responsive to determining that the first instruction operation has issued in the second entry, an indication that a corresponding second instruction operation is ready to issue may be provided.

Scheduler entries storing dependency index(es) for index-based wakeup

Techniques are disclosed relating to selection circuitry configured to select instruction operations to issue to one or more execution circuits of a processor. In some embodiments, an apparatus includes a plurality of execution circuits configured to perform one or more instruction operations. The apparatus may further include a plurality of instruction queues configured to store information indicative of the one or more instruction operations. In some embodiments, the apparatus may include a selection circuit configured to select a first plurality of instruction operations from a first instruction queue. The selection circuit may be configured to select a first instruction operation from the first plurality of instruction operations to issue to a first execution circuits. Further, the selection circuit may be configured to select a predesignated instruction operation of the first plurality of instruction operations to issue to a second execution circuit in response to a determination that no instruction operations in a second instruction queue are available to issue.

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Santa Clara, CA, United States of America

Gokul V Ganesan