Apple Inc.

Nvidia Corporation

Gokhan Avkarogullari

Jason P Jane

Richard Warren Schreyer

Michael Imbrogno

Alexander K Kan

Michal Valient

Michael J Swift

Peter F Holland

Patrick Y Law

Tatsuya Iwamoto

Yingying Tang

Luc R Semeria

Michael J E Swift

Guy Cote

Chaohao Wang

Paolo Sacchetto

John Harper

Joshua H Shaffer

Mahesh B Chappalli

Sheng Zhang

Koorosh Aflatooni

Roberto G Yepez

Tyson J Bergland

Yunhui Hou

Szu-Wen Huang

Anthony P DeLaurier

Kutty Banerjee

Kelvin C Chiu

Rohan Sanjeev Patil

Robert S Hartog

Sean P James

Terence M Potter

Jesse William Boettcher

Joseph P Bratt

Kenneth Christian Dyke

Steven L Petersen

Jeremy Sandmel

William E Bull

Nathaniel C Begeman

Sean Matthew Gies

Jenny Hu

Bartosz Ciechanowski

James R Montgomerie

Benjamin Bowman

Mehmet N Agaoglu

Pratik Chandresh Shah

Andrey Pokrovskiy

Rahul U Joshi

Alex Kan

Wanqing Xin

Eric O Sunalp

Charles Brissart

Yuhui Li

Lloyd A Cunningham

Michael J Wyrzykowski

An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

Displays with variable frame rates

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

Graphics surface addressing

The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command.

Task execution on a graphics processor using indirect argument buffers

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to access one or more entries in a set of multiple translation entries for pages of the surface space (where the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space) and translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.

Eliminating off screen passes using memoryless render target

In general, embodiments are disclosed for tracking and allocating graphics processor hardware resources. More particularly, a graphics hardware resource allocation system is able to generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters. The graphics hardware resource allocation system designate, based on the priority list, a first data master with a higher priority to submit work to the graphics processor compared to a second data master. The graphics hardware resource allocation system determines a stall counter value for the data master and generates a notification to pause work for the second data master based on the stall counter value.

Graphics hardware driven pause for quality of service adjustment

One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.

Low latency firmware command selection using a directed acyclic graph

An electronic device is provided. The electronic device includes a display that is configured to show content that includes a plurality of frames. The plurality of frames includes a first frame that is associated with a pre-transition value. The plurality of frames also includes a second frame that is associated with a current frame value that corresponds to a first luminance. Additionally, the electronic device is configured to determine an overdriven current frame value corresponding to a second luminance that is greater than the first luminance. The electronic device is also configured to display the second frame using the overdriven current frame value.

Overdrive for electronic device displays

One disclosed embodiment includes a method of graphics processing. The method includes receiving an indication to update a current frame on a display. A plurality of graphics command are determined to be associated with a next frame that replaces the current frame. A power-up command is generated based on the received indication, configured to cause GPU hardware to begin an initialization operation. The central processing unit processes the plurality of graphics command. Prior to completely process the plurality of graphics command, a power-up command is sent to a GPU firmware. The GPU firmware initializes the GPU hardware based on the power-up command. The processed plurality of graphics command is also transmitted to the GPU hardware. The GPU hardware executes the processed plurality of graphics command to render the next frame on the display.

Pro-active GPU hardware bootup

The disclosed concepts provide a method to generate and use a compound shader object. A compound shader object includes a shader's intermediate representation (IR) and one or more binary modules; each binary module configured to execute on one type of graphics processing unit (GPU) with a specific input state. One method includes receiving, through a public application programming interface (API), a request to execute a shader from an user-level application. At the framework level, if the request corresponds to one of the prior compiled binary modules, that module may be passed to a GPU for immediate execution via a system private interface. If the request does not correspond to one of the binary modules, the shader's IR module may returned to the requesting user-level application (which module would then have to be compiled before it may be sent to the GPU).

Compound shader object and use thereof

The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processor in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processor in response to passing the data structure to the second programming interface command.

One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

Texture not backed by real mapping

Power management techniques include a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.

Graphics processing unit providing thermal control via render quality degradation

In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Graphics hardware mode controls

Growing community of inventors

San Jose, CA, United States of America

Gokhan Avkarogullari