Hitachi, Ltd.

Renesas Technology Corp.

Goichi Yokomizo

Peter M Lee

Mikako Miyama

Junji Sato

Shiro Kamohara

Osamu Yamashiro

Masato Iwabuchi

Akio Yajima

Hirofumi Johnishi

Shigenori Otake

Chikako Yoshida

Munehiro Ogawa, Deceased

Hitoshi Sugihara

Toshiyuki Morioka

Masami Kinoshita

Akihisa Maruyama

Saburo Hojo

There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Simulation method and simulation program

The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation&equals;Act ) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.

Computer-readable storage media stored with a delay library for designing a semiconductor integrated circuit device

A semiconductor integrated circuit has a semiconductor internal circuit having a first power supply line and a second power supply line, wiring layers connected to a plurality of terminals of a first power supply and each having a predetermined inductance, and wiring layers connected to a plurality of terminals of a second power supply and each having a smaller inductance. Each of the former wiring layers has an inductor making a loop around the internal circuit.

Semiconductor integrated circuit and designing method thereof

A mixed mode simulation method and apparatus are provided for highly accurately simulating the total characteristics of a digital analyzed circuit portion and an analog analyzed circuit portion, which are both subjected to mixed mode simulation, in consideration of the influence exerted on the analog analyzed circuit portion by a current consumed by the digital analyzed circuit portion. More particularly, a current value of an equivalent circuit for current calculation modeled for providing the analog analyzed circuit portion with a current generated due to an operating state of the digital analyzed circuit portion realized by logic simulation is determined in synchronism with the logic simulation, and the equivalent circuit for current calculation derived thereby is composed with the analog analyzed circuit portion, and this composite circuit is subjected to circuit simulation.

Mixed mode simulation method and simulator

In verifying an LSI layout pattern, the whole layout pattern is converted into circuit data and a subcircuit to be verified is picked up and subjected to simulation. After converting the layout pattern into the transistor level circuit data, the transistor level circuit data is transformed into a logic gate level circuit data while judging a clocked gate included in the subcircuit. After picking up a subcircuit in a predetermined manner, an approximate load is connected to the interface port of the picked-up subcircuit.

Circuit simulation method for a circuit realized by an LSI layout

A circuit simulation method and apparatus for simulating the operation of semiconductor devices, including field effect transistors (FETs), on the basis of the mask layout pattern of each semiconductor device. A circuit simulation method is performed by a computer which includes a first step of determining an equivalent circuit of the semiconductor device from the mask layout patterns, and a second step of producing a signal indicative of the operation of the equivalent circuit determined by the first step. The equivalent circuit is determined by extracting resistive area patterns of the FETs and calculating resistance values of FET signal paths to obtain FET equivalent resistances. The resistive area patterns are divided into a series of rectangles which are converted to equivalent resistive elements to then be arranged so that an equivalent resistive value can be calculated.

Circuit simulation method for semiconductor device including field

Growing community of inventors

Nishitama, Japan

Goichi Yokomizo