Kioxia Corporation

Kabushiki Kaisha Toshiba

Goichi Ootomo

Tomoaki Suzuki

Fumihiko Sano

Takayoshi Shimazawa

Shigehiro Tsuchiya

A semiconductor device includes a first interface with a first channel at a first data transfer rate, a second interface with a second channel at a second data transfer rate slower than the first data transfer rate, a transfer circuit, and a processor. The processor is configured to, upon the first interface receiving a first data output command from a memory controller via the first channel, issue the first data output command via the second channel, in response to which a first memory chip connected to the second interface reads first data corresponding to the first data output command, and after a first predetermined amount of time has elapsed from the issuance of the first data output command, issue a first transfer start command via the second channel, in response to which the first data is transferred to the transfer circuit via the second channel.

Memory multichip package employing a frequency multiplying bridge chip

A semiconductor storage device includes a plurality of semiconductor memory chips and a bridge chip. The bridge chip includes a first interface connectable to an external memory controller that is external to the semiconductor storage device, a plurality of second interfaces connected to the semiconductor memory chips, and a controller. The controller is configured to, upon receiving, by the first interface, a first command sequence that includes a data transfer command to perform data transfer with one of the semiconductor chips and size information indicating a size of data to be transferred, start an operation to perform the data transfer, and end the operation, upon an amount of data that has been received by the first interface during the data transfer reaching the size indicated by the size information.

Signal processing in bridge chip in semiconductor storage device and memory system

A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Semiconductor device and method for controlling plural chips

A semiconductor storage device includes a bridge chip and memory chips connected to the bridge chip by a plurality of channels. The bridge chip includes a first delay circuit for setting the start of a first timing signal for a first memory chip output via a first channel and a second delay circuit for setting the start of for second timing signal for a second memory chip output via a second channel. A controller on the bridge chip controls at least one of the first and second delay circuits to adjust the start time of at least one of the first and second timing signals such that data sequences from the first and second memory chips will be aligned in time. The controller combines the data sequence from the first memory chip with the data sequence from the second memory chip to generate an interleaved serial sequence.

Semiconductor storage device, memory system, and method

According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.

Transceiver, bridge chip, semiconductor storage device, and method

The proposed variable length coder can detect the start codes appropriately, while reducing the circuit scale thereof. The variable length code decoding apparatus, comprises: an interface section (2) having a plurality of registers (R20, R21, R22) each having a predetermined number of bits, for storing variable length code data in each of the registers in first-in first-out status; a shift circuit (3) for receiving data transferred from a predetermined number of the adjacent registers of the interface section and for shifting the received data by a number of bits corresponding to an applied shift signal, to select a start code head; and a start code detecting circuit (6) for executing detection operation by receiving data supplied from a predetermined number of the adjacent registers of the interface section, by detecting presence or absence of a start code on the basis the received data kept in byte-aligned status to output a start code presence and absence signal, and by outputting a start code shift length signal indicative of a byte from which a head bit of the start code begins in unit of byte, the start code shift length signal being applied to the shift circuit as the shift signal.

Growing community of inventors

Kawasaki, Japan

Goichi Ootomo