Nxp B.v.

Nexperia B.v.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Godefridus Adrianus Maria Hurkx

Johannes Josephus Theodorus Marinus Donkers

Jan Sonsky

Jeroen Antoon Croon

Erwin Hijzen

Prabhat Agarwal

Stephan Heil

Stephan Bastiaan Simon Heil

Johannes Hubertus Antonius Brekelmans

Petrus Hubertus Cornelis Magnee

Abraham Rudolf Balkenende

Dave Willem Van Goor

Hugo Veenstra

Andreas Bernardus Maria Jansman

Tim Boettcher

Michiel Jos Van Duuren

Erik Petrus Antonius Maria Bakkers

Markus Mueller

Maurits Mario Nicolaas Storms

Stephen John Sque

Mark Andrzej Gajda

Michael Antoine Armand In 't Zandt

Erik Maria Van Bussel

Raymond Josephus Engelbart Hueting

Melanie Maria Hubertina Wagemans

A semiconductor device and a method of making the same is disclosed. The device includes a substrate having an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of contacts. At least one of the contacts includes an ohmic contact portion located on a major surface of the substrate. The ohmic contact portion comprises a first electrically conductive material. The at least one of the contacts also includes a trench extending down into the substrate from the major surface. The trench passes through the AlGaN layer and into the GaN layer. The trench is at least partially filled with a second electrically conductive material. The second electrically conductive material is a different electrically conductive material to the first electrically conductive material.

Gallium nitride/ aluminum gallium nitride semiconductor device and method of making a gallium nitride/ aluminum gallium nitride semiconductor device

A semiconductor device and a method of making the same are disclosed. The device includes a substrate including an AlGaN layer located on a GaN layer for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a plurality of electrical contacts located on a major surface of the substrate. The device further includes a plurality of passivation layers located on the major surface of the substrate. The plurality of passivation layers includes a first passivation layer of a first passivation material contacting a first area of the major surface and a second passivation layer of a second passivation material contacting a second area of the major surface. The first and second passivation materials are different passivation materials. The different passivation materials may be compositions of silicon nitride that include different proportions of silicon.

Semiconductor device and method of making a semiconductor device with passivation layers providing tuned resistance

A semiconductor device and a method of making the same. The device includes a substrate having an AlGaN layer located on one or more GaN layers, for forming a two dimensional electron gas at an interface between the AlGaN layer and the GaN layer. The device also includes a source contact. The device further includes a drain contact. The device also includes a gate contact located between the source contact and the drain contact. The gate contact includes a gate electrode. The gate contact also includes an electrically insulating layer located between the gate electrode and the AlGaN layer. The insulating layer includes at least one aperture for allowing holes generated during an off-state of the device to exit the device through the gate electrode.

Semiconductor device and method of making a semiconductor device

In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

Semiconductor heterojunction device

A heterojunction semiconductor device () comprising a substrate () and a multilayer structure disposed on the substrate. The multilayer structure comprising a first layer (), which comprises a first semiconductor disposed on top of the substrate, and a second layer (), which comprises a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer. The second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas () forms adjacent to the interface. The multilayer structure also comprising a passivation layer, which comprises a semiconductor passivation layer () disposed on top of the second layer. The heterojunction semiconductor device also includes a first terminal () electrically coupled to a first area of the heterojunction semiconductor device; and a second terminal () electrically coupled to a second area of the heterojunction semiconductor device. The second terminal () is electrically coupled to the semiconductor passivation layer such that electric charge can flow into the second terminal () from the semiconductor passivation layer ().

Disclosed is a semiconductor device comprising a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between a substrate and the second layer; and a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky electrode comprising a central region and an edge region, wherein the element comprises a conductive barrier portion located underneath said edge region only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode. A method of manufacturing such a semiconductor device is also disclosed.

Heterojunction semiconductor device and manufacturing method

An electronic component (), a first electrode (), a second electrode (), and a convertible structure () electrically coupled between the first electrode () and the second electrode (), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, wherein the convertible structure () comprises terminal portions () connected to the first electrode () and to the second electrode (), respectively, and comprises a line portion () between the terminal portions (), the line portion () having a smaller width or thickness than the terminal portions (), and wherein the convertible structure () is arranged with respect to the first electrode () and the second electrode () so that, in one of the at least two states, the line portion () has an amorphous 'Spot () extending along only a part of the line portion ().

Electronic component, and a method of manufacturing an electronic component

Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

GaN HEMTs and GaN diodes

A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.

Phase change memory (PCM) architecture and a method for writing into PCM architecture

The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body, whereby in the semiconductor body a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body, which is formed on the surface of the semiconductor device as a nano wire, whereupon a layer of a material is deposited over the semiconductor body and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire becomes exposed. According to the invention, a further layer of a further material is deposited over the semiconductor body with the nano wire before the layer of the material is deposited, which further layer is given a thickness smaller than the height of the nano wire, and a material is chosen for the further material such that, viewed in projection, the transition between the layer and the further layer is discernible before the nano wire is reached. In this way the nano wire can be exposed more accurately in the device. This increases the yield of useful devices.

Semiconductor device, and semiconductor device obtained by such a method

The invention relates to a semiconductor device () with a semiconductor body () comprising a bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions () comprises a nanowire (). The base region () has been formed from a layer () at the surface of the semiconductor body (); the other one () of the emitter or collector regions () has been formed in the semiconductor body () below the base region (). The emitter or collector region () comprising the nanowire () has been provided on the surface of the semiconductor body () such that its longitudinal axis extends perpendicularly to the surface.

Semiconductor device and method of manufacturing the same

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a vertical bipolar transistor with an emitter region, a base region and a collector region () of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region () comprises a first sub-region (A) bordering the base region () and a second sub-region (B) bordering the first sub-region (A) which has a lower doping concentration than the second sub-region (B), and the transistor is provided with a gate electrode () which laterally borders the first sub-region (A) and by means of which the first sub-region (A) may be depleted. According to the invention the collector region () borders the surface of the semiconductor body (), while the emitter region () is recessed in the semiconductor body (), and the collector region () forms part of a mesa structure () formed at the surface of the semiconductor body (). Such a device () has very favorable properties at high frequencies and high voltages and, moreover, is easy to manufacture. In a preferred embodiment the collector () comprises a nanowire () forming the mesa structure ().

The present invention relates to Current mirror for generating a constant mirror ratio, comprising an output transistor (Tt) having a base, an emitter and a collector, wherein a current flowing through the collector of said output transistor (T) constitutes an output current (I) of said current mirror and the collector of said output transistor (T) is connectable to an output circuit, a buffer transistor having a base, an emitter and a collector, wherein the emitter of the buffer transistor is connected to the base of the output transistor, a buffer current source for providing a fixed buffer current, wherein said buffer current source is connected to the collector of the buffer transistor, and a buffer base voltage control means having an input connected to the base of the output transistor and an output connected to the base of the buffer transistor, wherein the base voltage control means is adapted to controlling a voltage at the base of the buffer transistor in response to a current at the input of the buffer base voltage control means.

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Best, Netherlands

Godefridus Adrianus Maria Hurkx