Micron Technology Incorporated

Gloria Yang

Suraj J Mathew

Vinay Nair

Diem Thy N Tran

Raghunath Singanamalla

Fatma Arzum Simsek-Ege

Kris K Brown

Fawad Ahmed

Brent Keeth

Scott James Derner

Michael Amiel Shore

Jiewei Chen

Tracy D Evans

Fatma Arzum Slmsek-Ege

Jing Zhou

Systems associated with device temperature adjustment are described. A device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.

Device temperature adjustment

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

Vertical two-transistor single capacitor memory cells and memory arrays

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Memory cells and memory arrays

Growing community of inventors

Boise, ID, United States of America

Gloria Yang