International Business Machines Corporation

Glenwood S Weinert

Philip J Russell

Young O Kim

Lars W Liebmann

Mark Alan Lavin

According to the preferred embodiment, a method is provided for automatically coloring VLSI design elements for the purpose of assigning binary properties to the elements. The preferred method is particularly applicable for use generating phase shift mask designs from VLSI CAD datasets. The preferred method uses net coloring to automatically generate a data set of colored elements. The preferred method is not dependent on the order in which the elements are operated upon. The preferred method has the additional advantage of being able to automatically detect conflicts that prevent the VLSI design from being optimally colored. The preferred method is equally applicable to hierarchical VLSI databases with nested components and traditional flat databases. When applied the hierarchical databases, the preferred method provides element coloring with minimal data flattening required.

Automatic generation of phase shift masks using net coloring

A computer-based system and method is provided for building a representation of a hierarchical circuit design and component intrusions for the components making up the circuit design, as well as for verifying a design so-represented. For a subject hierarchical circuit design, a VLSI circuit design component representing a leaf design entity is isolated. A set of locations in the design where the component appears is determined. These locations represent unique instances of the leaf design entity. A set of links is associated with the VLSI circuit design component and the locations. The links connect various ones of the locations to one another to denote placement of the component within the hierarchical circuit design. To complete the representation, a set of instance counts is computed, one instance count for each location in the design where the component is represented. Each instance count denotes the number of instances of the component represented at the location with which the instance count is associated. Additional features of the invention include applicability to numerous types of design components (e.g., devices, nets, microprocessors, resistors), correspondence between each node of the inverse layout graph and a unique placement in the hierarchical circuit design, and the ability to determine intrusions according to any measure of proximity.

System and method for verifying a hierarchical circuit design

A computer-based system and method is provided for building subsets of a hierarchical circuit design. A VLSI circuit design component is stored in computer memory. The design component identifies a leaf design entity in the hierarchical circuit design. A set of placements is determined representing positions in the hierarchical circuit design where the VLSI circuit design component appears. The placements form a subset of instances of the leaf design entity. A set of links is created. The links are associated in memory with both the VLSI circuit design component and the placements, and connect various ones of the placements to one another to further denote placement of the VLSI circuit design component within the hierarchical circuit design. A subset list is appended to the VLSI circuit design component in computer memory. The subset list denotes the previously-determined subset and includes placements where the VLSI circuit design component is identified in the hierarchical circuit design. The identified placements may indicate exclusion of a particular instance of a design component from the hierarchical circuit design, or inclusion of a particular instance.

System and method for formulating subsets of a hierarchical circuit

A computer based system and method is provided for generating a design verification scheme for a hierarchical circuit design. A set of directives received describing design checks to be performed on a hierarchical circuit design. The directives are functionally decomposed into primitive functions required to perform them. A primary iteration level is established for each directive, and a data flow dependency is determined for the directives. Based on the data now dependency, a sequence or operations is organized. The operations are optimized in one or more ways to improve the efficiency of the design verification process. The optimized operations are coded into an application program which executes in a computer processor. The application program accesses the VLSI circuit design under review and performs the directives using the data structures allocated during schema generation.

Application generator for use in verifying a hierarchical circuit design

A computer-based system and method is provided for creating a representation of interconnections between VLSI circuit design components. A VLSI circuit design component identifying a leaf design entity is stored in memory. Placements in the design where the design component appears are stored in memory. A set of links is formed to connect placements to one another. The links further specify placement of the design component in the circuit design. The interconnections themselves are then computed. The interconnections denote where placements of the VLSI circuit design component instances are interconnected, and may specify any meaningful coupling, such as electrical conductivity, magnetic, or optical. The interconnections are represented by a nested net graph which includes a list of nets, and instance counts associated with the nets. The nested net graph may also include a second list, which specifies instances of lower nested nets contained in the nested net graph. The nested net graph may further include a shape-to-net table attached at the root of the nested net graph. The shape-to-net table defines a mapping from the VLSI circuit design component to a corresponding net. Also provided is a system and method for building interconnections using a bridge component, or bridge net. The bridge net denotes the interconnection between two nets derived from a pair of VLSI circuit design component instances.

Growing community of inventors

San Jose, CA, United States of America

Glenwood S Weinert