Agilent Technologies, Inc.

Keysight Technologies, Inc.

Glenn Wood

Brent Anthony Holcombe

Brock J LaMeres

David Eskeldson

Donald M Logelin

Michael Rytting

A method is provided for transmitting packets of a packet stream in real-time. The method includes sequentially writing packets in a retry buffer of a transmitting agent, the retry buffer including multiple contexts; sequentially transmitting the packets written in the retry buffer to a receiving agent, while continuing to sequentially write additional packets the retry buffer; receiving acknowledgements from the receiving agent when the receiving agent has successfully received the transmitted packets, while continuing to sequentially transmit the packets written in the retry buffer to the receive agent; receiving a retry request from the receiving agent when the receiving agent has not successfully received a transmitted packet; and retransmitting packets from the retry buffer to the receiving agent beginning with the transmitted packet not successfully received by the receiving agent, which resulted in the retry request, while continuing to sequentially write additional packets received from the transmitting agent in the retry buffer.

Retry buffer and method of performing retry operation using retry buffer

A method and apparatus for sequencing determines possible next states for respective possible previous states based upon resources, selects one of the possible next states as an actual next state based upon an actual previous state, and communicates the actual next state as the actual previous state.

Sequencer and method for sequencing

A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective cells of a sticky ONES (SONE) register previously initialized to all ZEROS. SZERO measures the unit interval of a ONE.

Unit interval discovery for a bus receiver

A probe apparatus has first and second access ports and a measurement port. The first and second access ports are adapted to be interposed in a test circuit. A voltage amplifier and a voltage splitter are adapted to present the second access port and the measurement port each with a voltage representative of a voltage received by the first access port.

Regenerator probe

A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose vertices are identified by threshold crossings offset for the voltage of interest and clocked by time delays offset from a clock time of interest. A first set of latches clocked by the time delays accumulates the state of signal behavior relative to the threshold voltages as it occurs, and their contents are subsequently transferred to a second set of latches at the start of a new clock cycle, allowing a new accumulation to begin and also allowing a detection logic circuit to operate on a unified and completed collection of indicators of what the just concluded description amounts to. The detection logic circuit responds to the combinations of latched indications to produce a signal corresponding to that description. The closed figure need not be a rectangle, and it may also serve as an indication that a signal went into a region that it should not have, e.g., an eye violation detector.

Bounding box signal detector

An isolation resistor is incorporated into the plunger of a probe tip spring pin by, for example, doping a ceramic that is used to form the plunger, or forming the plunger of first and second electrically coupled materials, at least a first of which has a resistivity sufficient to serve as an isolation resistor. Alternately, an isolation resistor is embedded in a printed circuit board trace that is used to couple either an upper or lower blind plated hole to a via. A probe tip spring pin is then inserted into the upper blind plated hole.

Incorporation of isolation resistor(s) into probes using probe tip spring pins

An electrical circuit detects a 'squelch,' or 'out-of-band,' state of a differential signal pair having a positive (&#x201c;p&#x201d;) signal line and a negative (&#x201c;n&#x201d;) signal line. In one embodiment of the invention, a first and a second comparator each have positive inputs driven by the positive and negative signal lines, respectively. The negative inputs of the comparators are driven by the outputs of separate digital-to-analog converters (DACs) which are set to a lower squelch threshold voltage. The outputs of the comparators then drive the inputs of a logical AND gate, the output of which indicates the current squelch state of the differential signal pair.

Differential signal squelch detection circuit and method

An electrical circuit generates both a differential data signal and a &ldquo;squelch,&rdquo; or &ldquo;out-of-band,&rdquo; state over a differential signal pair by employing common-mode logic (CML) technology. In one embodiment of the invention, a CML buffer having true and complementary (inverted) data outputs drive the differential data signal onto the positive ('p') and negative ('n') signal lines of the differential pair. To implement the squelch state, the true and complementary outputs of a two-input CML multiplexer are coupled with the corresponding outputs of the buffer. The data inputs of the multiplexer are driven by the data input signal driving the buffer, as well as the logical inversion of the data input signal. A squelch state signal then drives an input selector of the multiplexer to impress the squelch state over the differential signal pair when active.

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Colorado Springs, CO, United States of America

Glenn Wood