International Business Machines Corporation

Glenn Robert Miller

Arne Watson Ballantine

Jeffrey D Gilbert

Douglas Duane Coolbaugh

John J Ellis-Monaghan

James Albert Slinkman

Joseph R Greco

Jerome Brett Lasky

Donna Kaye Johnson

Toshihura Furukawa

Anthony K Stamper

Toshiharu Furukawa

Andrew Herbert Simon

Edward Crandal Cooney, Iii

Stephen Edward Greco

Nancy Anne Greco

Ronald A Warren

Ronald Dean Goldblatt

George A Dunbar, Iii

Frank V Liucci

Cheryl Faltermeier

David H Yao

Bruce A Root

Sophia Maumovna Ratenberg

A process for forming at least one interface region between two regions of semiconductor material. At least one region of dielectric material comprising nitrogen is formed in the vicinity of at least a portion of a boundary between the two regions of semiconductor material, thereby controlling electrical resistance at the interface.

Discontinuous dielectric interface for bipolar transistors

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

DC or AC electric field assisted anneal

A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.

Semiconductor temperature monitor

A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625&deg; C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the recrystallized layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Method of annealing copper metallurgy

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to a DC electric field.

DC electric field assisted anneal

A method of controlling the resistance and improving the low temperature tolerance of a polysilicon resistor is provided. The method of the present invention employs a second annealing step after one of the high temperature (about 800&deg; C. or above) device activation anneals. That is, the second annealing step can be used after source/drain activation, emitter activation or silicide formation. In accordance with the present invention, if a low temperature second annealing step below about 800&deg; C. is performed after the high temperature device activation anneal, the resistance of the resistor increases, whereas when the second annealing temperature is higher than about 800&deg; C., the resistance of the resistor decreases.

Two step anneal for controlling resistor tolerance

Growing community of inventors

Essex Junction, VT, United States of America

Glenn Robert Miller