Foveon, Inc.

Glenn Jay Keller

Shrinath Ramaswami

Richard B Merrill

Shri Ramaswami

Tatsuya Inui

Shigemi Yamazaki

Jonathan Yu

Carver A Mead

James E Tornes

Robert S Hannebauer

Alex Shiuh Wang

Ram Sena Bojja

SundaraSiva Rao Giduturi

An imaging array includes a plurality of rows of pixel sensors. A timing pattern generator generates timing pattern control signals and provide the timing pattern control signals to every row in the array. Timing pattern control signals generated during a timing pattern period directed to operate the pixel sensors in a selected row. A latched row driver circuit includes an enable latch in each row of the array responsive to a row address enable signal provided prior to the timing pattern period to gate the timing pattern control signals to the pixel sensors in the selected row at the start of the timing pattern period. A row address generator circuit is coupled to the timing pattern generator and to the enable latches in each row of the array to generate the row address enable signal for each selected row prior to the timing pattern period.

Pipelined row decoder topology for faster imager row decoding

In an array of multi-color vertical detector color pixel sensors, a readout wiring architecture includes a transfer transistor for each individual color detector. In first and second rows in a first column, the first, second, and third color transfer transistor gates are coupled, respectively, to the first, second, and third row-select lines. In a first row in a second column, the first color transfer transistor gate is coupled to the second row-select line, the second color transfer transistor gate is coupled to the first row-select line, and the third color transfer transistor gate is coupled to the third row-select line. In a second row in the second column, the first color transfer transistor gate is coupled to the first row-select line, the second color transfer transistor gate is coupled to the third row-select line, and t the third color transfer transistor gate is coupled to the second row-select line.

Sub-sampled color channel readout wiring for vertical detector pixel sensors

A switchable amplifier and comparator circuit includes an operational amplifier having an inverting input, a non-inverting input, a first differential output and a second differential output, the first differential output switchably coupled to the inverting input and the second differential output switchably coupled to the non-inverting input. A first feedback capacitor is coupled to the inverting input and switchably coupled to the first differential output, a second feedback capacitor is coupled to the non-inverting input and switchably coupled to the second differential output. A capacitive load is switchably coupled between the first differential output and the second differential output. A diode clamp circuit is switchably coupled between the first differential output and the second differential output. A resistive load is switchably coupled between the first differential output and the second differential output.

Combined programmable gain amplifier and comparator for low power and low area readout in image sensor

In an array containing rows and columns of multi-color vertical detector color pixel sensors disposed in a rows and columns of the array, a readout wiring architecture includes a plurality of row-select lines for each row of the array, equal to the number of colors in the vertical detector color pixel sensors, an individual column line for each column, a transfer transistor for each individual color detector coupled between a color detector and a column line associated with the column in which the color detector is disposed. Each transfer transistor has a gate coupled to one of the plurality of row-select lines in a row in which the vertical detector color pixel sensor is disposed. The gates of at least some of the transfer transistors in each row for each color detector in adjacent columns of the array are coupled to different ones of the row-select lines for that row.

A method for performing color density filtering of images captured in a digital camera having a mechanical shutter and an imaging array including a plurality of pixels each including different color sensors aligned with each other, including opening the mechanical shutter, resetting all of the color sensors in each pixel by asserting a row reset signal, separately asserting color-select signals for each color after the mechanical shutter is opened, independently starting exposure for each different color sensor at a color sensor exposure start time by de-asserting its color select signal, the exposure start time for each different color sensor being a function of a color density filter function, closing the mechanical shutter, and reading color exposure values from the color sensors by separately asserting color-select signals after the mechanical shutter has closed, the reading being unrelated to the start times for the color sensors.

Electronically controlled graduated density filters in stacked image sensors

In a digital camera having an imaging array including a plurality of pixels arranged in rows and columns, the digital camera having a mechanical shutter, a method for performing neutral density filtering of images captured by the imaging array, the method comprising opening the mechanical shutter, operating each row in the array by resetting all of the pixel sensors in the row, starting exposure for all of the pixel sensors in the row, closing the mechanical shutter, reading pixel values from the pixels in the array after the mechanical shutter has closed at a time unrelated to a time at which any pixel-select signal was de-asserted, and wherein the interval of time between starting exposure for all of the pixel sensors in the row and closing the mechanical shutter for each row a function of a neutral density filter function applied to an image to be captured.

An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output.

CMOS pixel sensor with depleted photocollectors and a depleted common node

Vertical-color-filter pixel sensors having simplified wiring and reduced transistor counts are disclosed. In an embodiment, a single line is used for reference voltage, pixel reset voltage, and column-output signals in a VCF pixel sensor. In another embodiment, row-reset signals and row-enable signals are sent across a line that is shared between adjacent rows in an array of VCF pixel sensors. The present invention also provides an optimized layout for a VCF pixel sensor with shared row-reset, row-enable, reference voltage and column-output lines as well as a VCF pixel sensor in which source-follower voltage, source-follower amplifier voltage and row-enable signals all share a common line. These combined line embodiments can be used with a single column-output line as well as two row-enable lines. The embodiments can also be implemented in a VCF pixel sensor without a row-enable transistor.

Growing community of inventors

West Chester, PA, United States of America

Glenn Jay Keller