Intel Corporation

Other

Glenn J Hinton

Andrew F Glew

David B Papworth

Michael A Fetterman

Robert P Colwell

Haitham H Akkary

Kris G Konigsfeld

Paul D Madland

Raj K Ramanujan

Ronak Singhal

Jeffrey M Abramson

David J Sager

Robert W Martell

Bret L Toll

Per H Hammarlund

Michael D Upton

Ashwani Kumar Gupta

Patrice L Roussel

Stephan Jourdan

David Zimmerman

Bradley D Hoyt

Subramanian Natarajan

Shreekant S Thakkar

Rajat Agarwal

Thomas D Fletcher

Brent Ralph Boswell

Sunil R Shenoy

Reynold V D'Sa

Karol F Menezes

Vincent J Zimmer

Michael A Rothman

Avinash Sodani

Shantanu R Gupta

Chan W Lee

Mohan J Kumar

Darrell D Boggs

Kai Cheng

Mark Doran

Eric Dahlen

Muthukumar Swaminathan

John G Holm

Michael Kinney

Sebastien Hily

Deborah T Marr

Mandar S Joshi

Robert F Krick

Dimitrios Ziakas

Bassam N Coury

Michael Cornaby

William Rash

Dale J Juenemann

Mark T Bohr

Martin Guy Dixon

Arvind A Kumar

Wilfred Gomes

Rajesh Kumar

Robert S Chappell

Belliappa Manavattira Kuttanna

Adrian C Moga

Scott D Hahn

Robert Milstrey

R Scott Tetrick

Johan G Van De Groenendaal

Frederick J Pollack

Gilbert A Neiger

Rajesh M Sankaran

Sean Stephen Eilert

Sanjeev N Trika

Shubhendu Sekhar Mukherjee

Richard A Uhlig

Barnes Cooper

Blaise B Fanning

Anil Vasudevan

Steven E Wells

Yen-Cheng Liu

Sanjay Kumar

Shekoufeh Qawami

Nitin V Sarangdhar

Konrad K Lai

Stephen Anthony Fischer

Matthew C Merten

Joseph Nuzman

Frank T Hady

Eric A Sprangle

Alaa R Alameldeen

Rodney R Rozman

Yadong Li

Sailesh Kottapalli

Michael W Rhodehamel

Rajesh S Parthasarathy

Amber D Huffman

Leena K Puthiyedath

Nicholas G Samra

Arijit Biswas

Hermann Gartler

Subramanya R Dulloor

Jeanna N Matthews

Wayne Alan Downer

James A Boyd

Rohit A Vidwans

Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.

Device, method and system for providing a stacked arrangement of integrated circuit dies

A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

Dynamic partial power down of memory-side cache in a 2-level memory hierarchy

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.' In one embodiment, the &#x201c;near memory&#x201d; is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Apparatus and method for implementing a multi-level memory hierarchy having different operating modes

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'

Apparatus and method for implementing a multi-level memory hierarchy

A disclosed example method to suspend and resume a device includes: after detecting a low-power suspend mode request, determining a storage performance of the device to store suspend state data; based on the storage performance of the device, setting a suspend flag to indicate a low-power suspend mode to a processor platform; when resuming from the low-power suspend mode, confirming a setting of a resume flag from the processor platform, the resume flag to notify an operating system to resume from the low-power suspend mode; and when the resume flag is set, restoring state data corresponding to an operating system context from a non-volatile dual-purpose system and storage memory.

Methods and apparatus to suspend and resume computing systems

In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.

QoS based binary translation and application streaming

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes 'near memory' comprising memory made of volatile memory, and 'far memory' comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as 'main memory' to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

Two-level system main memory

A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M&#xd7;N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M&#xd7;N-bits of the line of memory.

Multiple register memory access instructions, processors, methods, and systems

Growing community of inventors

Portland, OR, United States of America

Glenn J Hinton