Integrated Device Technology, Inc.

Ip-first, LLC

Glenn Henry

Terry J Parks

Rodney E Hooker

Darius Gaskins

Gerard M Col

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

Selective interrupt suppression

An apparatus in a microprocessor for selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count of the number of accesses to the prefetched cache line and N second counts of the number of accesses to N lines of a replacement candidate set of the cache selected by the prefetched cache line address are maintained. When another prefetch is requested, if the first count is greater than the smaller of the N second counts, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded. In a second embodiment, a count of accesses to the replacement candidate line is maintained. When another prefetch is requested, if the count is greater than a programmable threshold value, the candidate prefetched cache line is retired into the cache; otherwise the prefetched cache line is discarded.

Microprocessor, apparatus and method for selective prefetch retire

A microprocessor with an apparatus for alleviating the need to maintain coherency between cache line status of a store buffer and a response buffer each storing the same cache line address is disclosed. The store buffers include match bits. When a store operation requires a response buffer to be allocated (e.g., to receive a cache line implicated by a store miss of a write-allocate cache or to obtain exclusive ownership of a shared cache line hitting in the cache), control logic populates the match bits to specify which of the response buffers was allocated. Control logic updates the cache line status in the allocated response buffer as status-altering events occur, which is subsequently used to update the cache, thereby alleviating the need for the store buffer to maintain the cache line status. If the store address matches an already-allocated response buffer, that response buffer is specified in the match bits.

Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status

An apparatus and method for improving descriptor load time in a microprocessor are provided. The method and apparatus provide an instruction sequence which loads a selector, forwards a table index (TI) bit retrieved from the selector for use by the next instruction which loads the descriptor. Forwarding of the table index bit to a register file selects between a global descriptor table and a local descriptor table for loading the descriptor, without intervening instructions or clock cycles. The forwarded table index selectively addresses either the global descriptor table or the local descriptor table only when a descriptor load instruction is immediately preceded by a selector load instruction.

Apparatus and method for fast forwarding of table index (TI) bit for

A method and apparatus for handling interrupts after transition of a mask flag is provided. In x86 processors, if the IF flag is cleared, interrupts are to be masked. If the IF flag is set, interrupts are to be handled. However, if the IF flag transitions from a clear state to a set state, and the instruction which sets the IF bit is an STI instruction, then a pending interrupt is to be delayed for one instruction, unless the following instruction is a floating point instruction, and then the interrupt is to be handled immediately. The invention allows an interrupt to cause a branch to an exception handler if the IF bit is set. The exception handler determines whether the prior instruction was an STI instruction, and whether the prior state of the IF bit was clear. If both these conditions are true, the exception handler branches back to the main program. If either condition is not true, the exception handler branches to an interrupt service routine.

Apparatus and method for managing interrupt delay associated with mask

A method and apparatus for tracking the fill status of sub cache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.

Method and apparatus for sub cache line access and storage allowing

An apparatus and method for improving the execution speed of particular micro instruction sequences is provided, and which allows for exception handling of the micro instruction sequences, as needed. During execution of a micro instruction sequence, particular registers are allowed to be overwritten prior to completion of the entire micro instruction sequence. A tracking mechanism is provided which tracks which registers are overwritten, and restoration logic is provided which stores the 'old' contents of the particular registers. If the micro instruction sequence cannot complete, due to a fault, for example, the tracking mechanism indicates which registers have been overwritten, and the restoration logic provides the 'old' values to be restored.

Apparatus and method for of register changes during execution of a micro

An apparatus and method for organizing a data array within a cache system to store a plurality of physical pages of data. A single data array is associated with a plurality of tag arrays, each tag array tracking a page size portion of the data array. Indexing into each of the tag arrays is accomplished using the page index from either of the virtual address or the physical address. In addition, selection of indexed tags from the tag arrays is performed by array selection logic which utilizes portions of either of the virtual page number or the physical page number.

Cache array select logic allowing cache array size to differ from

An apparatus for locating exception correction routines within a control ROM of a microprocessor. A control ROM generates micro instructions that are addressable by a microprocessor. A translator generates micro instructions that do not have addresses which may be referenced. Error correction routines must be provided for micro instructions whether they are provided by a translator, or by a control ROM. Exception correction routines are stored in a control ROM at fixed offsets relative to the micro instructions for which they provide correction. For translator generated micro instructions, an address corresponding to an appropriate exception correction routine is provided to the control ROM and latched. This address may later be read from the latch should an exception condition occur.

Method and apparatus for locating exception correction routines

An apparatus for storing selectors directly into segment registers within a single processor cycle. New selectors are stored into addressable segment registers prior to being validated. Old selectors which are shifted into temporary register space prior to being overwritten. If a selector fails validation tests, and requires restoration, the old selector is shifted back into the appropriate segment register thereby restoring the state of the selector.

Method and apparatus for selector storing and restoration

A method and apparatus for tracking the fill status of subcache line locations during a cache line fill operation is provided. The tracking system monitors the data cycles of a burst read during a cache line fill, and sets indicators pertaining to which of the sub cache lines within the cache line have been filled. Cache control utilizes the indicators to make those sub cache lines that have been filled available to a processing system as they are filled, rather than waiting for the entire cache line to be filled. Data is stored directly into sub cache line locations without requiring a cache line buffer.

An apparatus and method for handling exceptions during execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation, and an execution unit for executing the micro instruction sequence. A counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is incremented/decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from the counter which indicates that all of the string has been operated upon, e.g., if the counter reaches zero. If exceptions occur during the operation of the translator generated string instructions, the value of the counter is stored in a temporary register, the string operation is ended as if the counter reached zero, the exception is handled, the value of the counter is restored, and the string operation is restarted.

Apparatus and method for processing exceptions during execution of

An apparatus and method for improving the execution of string instructions is provided. The apparatus includes a translator which repetitively generates a micro instruction sequence applicable to the particular string operation to be performed, and an execution unit for executing the micro instruction sequence. In addition, a counter is provided to hold a count value corresponding to the number of times the micro instruction sequence is to be executed, and is decremented each time the sequence is executed. The translator continues to generate the micro instruction sequence until receiving a signal from a counter which indicates that all of the string has been operated upon. In addition, the execution unit receives the signal from the counter and tests subsequent micro instructions to determine whether they are associated with string instructions. If so, the execution unit performs NOPs in place of those micro instructions.

Method and apparatus for repetitive execution of string instructions

An apparatus and method for improving the execution speed of register generic micro instructions within a pipeline microprocessor is provided. The microprocessor includes descriptor compare logic which monitors references to last used segment registers, and maintains the base address of the last used segment. As holes are created by later register generic micro instructions, the descriptor compare logic compares operands with that of the last accessed segment register. When an operand of the present micro instruction is the same as the last accessed segment register, the descriptor compare logic provides a pipeline release signal which releases the base address associated with the last accessed segment register directly to the following stage in the pipeline, thereby effectively eliminating the register stage of the pipeline, and the associated hole in the pipeline, for the present micro instruction.

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Austin, TX, United States of America

Glenn Henry